CY7C1316AV18 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1316AV18 Datasheet PDF : 20 Pages
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CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
Application Example[1]
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the DDR-II. In the single clock mode, CQ is generated with
respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. The DLL can also be reset by slowing the cycle time
of input clocks K and K to greater than 30 ns.
DQ
A
SRAM#1
ZQ
CQ/CQ#
LD# R/W# C C# K K#
R = 250ohms
SRAM#2
ZQ
DQ
CQ/CQ#
A LD# R/W# C C# K K#
R = 250ohms
DQ
BUS
Addresses
MASTER Cycle Start#
(CPU
R/W#
or
Return CLK
ASIC) Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
LD R/W
DQ
DQ
Write Cycle:
L-H
Load address; wait one cycle; input write data on consecutive K
and K rising edges.
L L D(A1)at K(t + 1) ↑ D(A2) at K(t + 1) ↑
Read Cycle:
L-H
Load address; wait one and a half cycle; read data on consec-
utive C and C rising edges.
L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑
NOP: No Operation
L-H H X High-Z
High-Z
Standby: Clock Stopped
Stopped X X Previous State Previous State
Burst Address Table (CY7C1318AV18,
CY7C1320AV18)
First Address (External)
X..X0
X..X1
Second Address (Internal)
X..X1
X..X0
Notes:
1. The above application shows two DDR-II used.
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. On CY7C1318AV18 and CY7C1320AV18, A” represents address location latched by the devices when transaction was initiated and A2 represents the addresses
sequence in the burst. On CY7C1316AV18, A1 represents A +‘0’ and A2 represents A +‘1.’
5. “t” represents the cycle at which a Read/Write operation is started. t+1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document #: 38-05499 Rev. *B
Page 7 of 20
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