CY7C1316AV18 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1316AV18 Datasheet PDF : 20 Pages
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CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Thermal Resistance[16]
Parameter
Description
Test Conditions
ΘJA Thermal Resistance (Junction to Ambient) Test conditions follow standard test
ΘJC
Thermal Resistance (Junction to Case)
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
165 FBGA Package Unit
16.7
°C/W
2.5
°C/W
AC Test Loads and Waveforms
VREF
OUTPUT
Device
Under
Test
ZQ
(a)
0.75V
Z0 = 50Ω
RQ =
250Ω
VREF
RL = 50Ω
VREF = 0.75V
OUTPUT
Device
Under ZQ
Test
INCLUDING
JIG AND
SCOPE
VREF = 0.75V
0.75V
R = 50Ω
RQ =
250Ω
(b)
5 pF 0.25V
[15]
ALL INPUT PULSES
1.25V
0.75V
Slew Rate = 2V/ns
Switching Characteristics Over the Operating Range [17,18]
Cypress Consortium
Parameter Parameter
Description
250 MHz 200 MHz 167 MHz
Min. Max. Min. Max. Min. Max. Unit
tCYC
tKH
tKL
tKHKH
tKHKH
tKHKL
tKLKH
tKHKH
K Clock and C Clock Cycle Time
4.0 6.3 5.0 7.9 6.0 8.4 ns
Input Clock (K/K and C/C) HIGH
1.6 – 2.0 – 2.4 – ns
Input Clock (K/K and C/C) LOW
1.6 – 2.0 – 2.4 – ns
K Clock Rise to K Clock Rise and C to C Rise (rising 1.8 – 2.2 – 2.7 – ns
edge to rising edge)
tKHCH
tKHCH
Set-up Times
K/KClockRisetoC/CClockRise(risingedgetorisingedge) 0.0 1.8 0.0 2.3 0.0 2.8 ns
tSA
tSA
tSC
tSC
tSCDDR
tSC
tSD
tSD
Hold Times
Address Set-up to K Clock Rise
0.5 – 0.6 – 0.7 – ns
Control Set-up to Clock (K, K) Rise (LD, R/W)
0.5 – 0.6 – 0.7 – ns
Double Data Rate Control Set-up to Clock (K, K) 0.35 – 0.4 – 0.5 – ns
Rise (BWS0, BWS1, BWS2, BWS3)
D[X:0] Set-up to Clock (K and K) Rise
0.35 – 0.4 – 0.5 – ns
tHA
tHA
tHC
tHC
tHCDDR
tHC
tHD
tHD
Output Times
Address Hold after Clock (K and K) Rise
0.5 – 0.6 – 0.7 – ns
Control Hold after Clock (K and K) Rise (LD, R/W) 0.5 – 0.6 – 0.7 – ns
Double Data Rate Control Hold after Clock (K and 0.35 – 0.4 – 0.5 – ns
K) Rise (BWS0, BWS1, BWS2, BWS3)
D[X:0] Hold after Clock (K and K) Rise
0.35 – 0.4 – 0.5 – ns
tCO
tDOH
tCHQV
tCHQX
C/C Clock Rise (or K/K in single clock mode) to Data Valid – 0.45 – 0.45 – 0.50 ns
Data Output Hold after Output C/C Clock Rise
(Active to Active)
–0.45 – –0.45 – –0.50 – ns
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
– 0.45 – 0.45 – 0.50 ns
Notes:
17. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
18. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
Document #: 38-05499 Rev. *B
Page 10 of 20
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