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RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

Cypress Semiconductor 

In systems where multiple SRAMs with multiple RPS# lines are used, a dummy read operation will have to be

performed on every SRAM on the board. Below is an example sequence of events that can be performed

before valid access can be performed on the SRAM.

1) Initialize the Memory Controller

2) Assert RPS# Low for each of the memory devices

Note:

For all devices with x9 bus configuration, the following sequence needs to be performed:

1) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 low respectively and perform dummy

read.

2) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 high respectively and perform dummy

read.

If the customer has the trigger conditions met during normal access to the memory then there is no workaround

at this point.

K

/K

/RPS

Address A

DataOut (Q)

WE#

Address A

DataOut (Q)

QDRII Operation

C

E

G

Q(A)

Q(A+1) Q(C)

Q(C+1)

Q(E) Q(E+1)

Dummy Read

DDRII Operation

C

E

G

DQ(A)

DQ

(A+1)

DQ(C)

DQ

(C+1)

DQ(E)

DQ

(E+1)

Figure 4. Dummy Read Implementation

• FIX STATUS

The fix has been implemented on the new revision and is now available. The new revision is an increment of

the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new

revision after the fix.

3. JTAG Mode Issue

• ISSUE DEFINITION

If the input clock (K Clock) is left floating when the device is in JTAG mode, spurious high frequency noise on

this input can be interpreted by the device as valid clocks. This could cause the impedance matching circuitry

(ZQ) on the QDR/DDR devices to periodically load itself with incorrect values. These incorrect values in the

ZQ register could force the outputs into a High-Impedance state. The ZQ circuitry requires at least 1000 valid

K clock cycles to drive the outputs from high impedance to low impedance levels.

• PARAMETERS AFFECTED

Document #: 001-06217 Rev. *C

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