CY7C1212H-133AXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1212H-133AXI Datasheet PDF : 15 Pages
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CY7C1212H
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Truth Table[2, 3, 4, 5, 6, 7]
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
0
Max.
40
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Next Cycle Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV OE
Unselected
None
HXX L
X
L
X
X
DQ
Tri-State
Unselected
None
LXH L
L
X
X
X
Tri-State
Unselected
None
LLX L
L
X
X
X
Tri-State
Unselected
None
LXH L
H
L
X
X
Tri-State
Unselected
None
LLX L
H
L
X
X
Tri-State
Begin Read
External
LHL
L
L
X
X
X
Tri-State
Begin Read
External
LHL
L
H
L
X
X
Tri-State
Continue Read Next
XXX L
H
H
L
H
Tri-State
Continue Read Next
XXX L
H
H
L
L
DQ
Continue Read Next
HXX L
X
H
L
H
Tri-State
Continue Read Next
HXX L
X
H
L
L
DQ
Suspend Read Current
XXX L
H
H
H
H
Tri-State
Suspend Read Current
XXX L
H
H
H
L
DQ
Suspend Read Current
HXX L
X
H
H
H
Tri-State
Suspend Read Current
HXX L
X
H
H
L
DQ
Begin Write
Current
XXX L
H
H
H
X
Tri-State
Write
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA,BWB),
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package.
6. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05668 Rev. *B
Page 5 of 15
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