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CY7C1061AV33-12ZXI Datasheet PDF : 10 Pages
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CY7C1061AV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND [3] ... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State [3] ...................................–0.5V to VCC + 0.5V
DC Input Voltage [3] ............................... –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 0.3V
DC Electrical Characteristics (Over the Operating Range)
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage IOH = –4.0 mA
VOL
Output LOW Voltage IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage [3]
IIX
Input Leakage Current GND < VI < VCC
IOZ
Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating
VCC = max,
Commercial
Supply Current
f = fmax = 1/tRC
Industrial
ISB1
Automatic CE
CE2 <= VIL, max VCC, CE > VIH
Power-down Current VIN > VIH or
—TTL Inputs
VIN < VIL, f = fmax
ISB2
Automatic CE
CE2 <= 0.3V
Commercial/
Power-down Current max VCC,
Industrial
—CMOS Inputs
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
–10
Min
Max
2.4
0.4
2.0 VCC + 0.3
–0.3
0.8
–1
+1
–1
+1
275
275
70
–12
Unit
Min
Max
2.4
V
0.4
V
2.0 VCC + 0.3 V
–0.3
0.8
V
–1
+1
µA
–1
+1
µA
260 mA
260 mA
70
mA
50
50
mA
Capacitance [4]
Parameter
Description
Test Conditions
TSOP II
FBGA
Unit
CIN
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V
6
8
pF
COUT
IO Capacitance
8
10
pF
AC Test Loads and Waveforms [5]
OUTPUT
50Ω
VTH = 1.5V
3.3V
R1 317 Ω
Z0 = 50Ω
(a)
30 pF* * Capacitive Load consists of all com-
ponents of the test environment.
3.3V
ALL INPUT PULSES
90%
90%
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE (b)
R2
351Ω
GND
10%
10%
Rise time > 1V/ns
(c)
Fall time:
> 1V/ns
Notes
3. VIL (min) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
Document #: 38-05256 Rev. *G
Page 3 of 10
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