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A386DX

32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT

Intel 

Intel386TM DX MICROPROCESSOR

2 BASE ARCHITECTURE

2 1 INTRODUCTION

The Intel386 DX consists of a central processing

unit a memory management unit and a bus inter-

face

The central processing unit consists of the execu-

tion unit and instruction unit The execution unit con-

tains the eight 32-bit general purpose registers

which are used for both address calculation data

operations and a 64-bit barrel shifter used to speed

shift rotate multiply and divide operations The

multiply and divide logic uses a 1-bit per cycle algo-

rithm The multiply algorithm stops the iteration

when the most significant bits of the multiplier are all

zero This allows typical 32-bit multiplies to be exe-

cuted in under one microsecond The instruction unit

decodes the instruction opcodes and stores them in

the decoded instruction queue for immediate use by

the execution unit

The memory management unit (MMU) consists of a

segmentation unit and a paging unit Segmentation

allows the managing of the logical address space by

providing an extra addressing component one that

allows easy code and data relocatability and effi-

cient sharing The paging mechanism operates be-

neath and is transparent to the segmentation pro-

cess to allow management of the physical address

space Each segment is divided into one or more 4K

byte pages To implement a virtual memory system

the Intel386 DX supports full restartability for all

page and segment faults

Memory is organized into one or more variable

length segments each up to four gigabytes in size A

given region of the linear address space a segment

can have attributes associated with it These attri-

butes include its location size type (i e stack code

or data) and protection characteristics Each task

on an Intel386 DX can have a maximum of 16 381

segments of up to four gigabytes each thus provid-

ing 64 terabytes (trillion bytes) of virtual memory to

each task

The segmentation unit provides four-levels of pro-

tection for isolating and protecting applications and

the operating system from each other The hardware

enforced protection allows the design of systems

with a high degree of integrity

The Intel386 DX has two modes of operation Real

Address Mode (Real Mode) and Protected Virtual

Address Mode (Protected Mode) In Real Mode the

Intel386 DX operates as a very fast 8086 but with

32-bit extensions if desired Real Mode is required

primarily to setup the processor for Protected Mode

operation Protected Mode provides access to the

sophisticated memory management paging and

privilege capabilities of the processor

Within Protected Mode software can perform a task

switch to enter into tasks designated as Virtual 8086

Mode tasks Each such task behaves with 8086 se-

mantics thus allowing 8086 software (an application

program or an entire operating system) to execute

The Virtual 8086 tasks can be isolated and protect-

ed from one another and the host Intel386 DX oper-

ating system by the use of paging and the I O Per-

mission Bitmap

Finally to facilitate high performance system hard-

ware designs the Intel386 DX bus interface offers

address pipelining dynamic data bus sizing and di-

rect Byte Enable signals for each byte of the data

bus These hardware features are described fully be-

ginning in Section 5

2 2 REGISTER OVERVIEW

The Intel386 DX has 32 register resources in the

following categories

 General Purpose Registers

 Segment Registers

 Instruction Pointer and Flags

 Control Registers

 System Address Registers

 Debug Registers

 Test Registers

The registers are a superset of the 8086 80186 and

80286 registers so all 16-bit 8086 80186 and

80286 registers are contained within the 32-bit In-

tel386 DX

Figure 2-1 shows all of Intel386 DX base architec-

ture registers which include the general address

and data registers the instruction pointer and the

flags register The contents of these registers are

task-specific so these registers are automatically

loaded with a new context upon a task switch opera-

tion

The base architecture also includes six directly ac-

cessible segments each up to 4 Gbytes in size The

segments are indicated by the selector values

placed in Intel386 DX segment registers of Figure

2-1 Various selector values can be loaded as a pro-

gram executes if desired

8

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