CY7C027V-15AXI Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C027V-15AXI

3.3 V 32 K / 64 K × 16 / 18 Dual-Port Static RAM

Cypress Semiconductor 

CY7C027V/027AV/028V

CY7C037AV/038V

Switching Waveforms

Figure 4. Read Cycle No. 1 (Either Port Address Access) [21, 22, 23]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

tOHA

CE and

LB or UB

OE

DATA OUT

ICC

CURRENT ISB

ADDRESS

Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [21, 24, 25]

tACE

tDOE

tLZOE

tLZCE

tPU

tHZCE

tHZOE

DATA VALID

tPD

Figure 6. Read Cycle No. 3 (Either Port) [21, 23, 24, 25]

tRC

tAA

tOHA

UB or LB

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

tHZCE

tHZCE

Notes

21. R/W is HIGH for read cycles.

22. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.

23. OE = VIL.

24. Address valid prior to or coincident with CE transition LOW.

25. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

Document Number: 38-06078 Rev. *G

Page 11 of 24

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