CY7C027V-15AXI Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C027V-15AXI

3.3 V 32 K / 64 K × 16 / 18 Dual-Port Static RAM

Cypress Semiconductor 

CY7C027V/027AV/028V

CY7C037AV/038V

Switching Characteristics(continued)

Over the Operating Range

Parameter [13]

Description

Busy Timing[19]

tBLA

BUSY LOW from address match

tBHA

BUSY HIGH from address

mismatch

tBLC

BUSY LOW from CE LOW

tBHC

BUSY HIGH from CE HIGH

tPS

Port setup for priority

tWB

R/W HIGH after BUSY (Slave)

tWH

R/W HIGH after BUSY HIGH (Slave)

tBDD[20]

BUSY HIGH to data valid

Interrupt Timing[19]

tINS

INT set time

tINR

INT reset time

Semaphore Timing

tSOP

SEM flag update pulse (OE or

SEM)

tSWRD

tSPS

tSAA

SEM flag write to read time

SEM flag contention window

SEM address access time

-15

Min

Max

CY7C027V/027AV/028V/

CY7C037AV/CY7C038V

-20

Min

Max

–

15

–

20

–

15

–

20

–

15

–

20

–

15

–

16

5

–

5

–

0

–

0

–

13

–

15

–

–

15

–

20

–

15

–

20

–

15

–

20

10

–

10

–

5

–

5

–

5

–

5

–

–

15

–

20

-25

Min

Max

–

20

–

20

–

20

–

17

5

–

0

–

17

–

–

25

–

20

–

20

12

–

5

–

5

–

–

25

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Notes

19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 waveform.

20. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).

Document Number: 38-06078 Rev. *G

Page 10 of 24

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