CY62128VLL-70ZAC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY62128VLL-70ZAC Datasheet PDF : 12 Pages
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1*CY62128V Family
CY62128V Family
Features
• Low voltage range:
— 2.7V–3.6V (CY62128V)
— 2.3V–2.7V (CY62128V25)
— 1.6V–2.0V (CY62128V18)
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62128V family is composed of three high-performance
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE1), an active HIGH Chip Enable (CE2), an active
128K x 8 Static RAM
LOW Output Enable (OE) and three-state drivers. These de-
vices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Writing to the device is accomplished by taking Chip Enable
one (CE1) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking Chip En-
able one (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Logic Block Diagram
A0
A1
A2
AA34
A5
A6
AA78
CE1
CE2
WE
OE
INPUT BUFFER
512x 256x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
62128V-1
Pin Configurations
Top View
SOIC
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
62128V-2
A4
16
A5
15
A6
14
A7
13
A12
12
A14
11
A16
10
NC
9
VCC
8
A15
7
CE2
6
WE
5
A13
4
A8
3
A9
2
A11
1
Reverse TSOP I
Top View
(not to scale)
17 A3
18 A2
19 A1
20 A0
21 I/O0
22 I/O1
23 I/O2
24 GND
25 I/O3
26 I/O4
27 I/O5
28 I/O6
29 I/O7
30 CE1
31 A10
32 OE
A11
25
A9
26
A8
2267
A13
28
WE 29
CE2 30
A15
31
VCC
32
NC 1
A16
2
A14
3
A12
4
A7 5
A6 6
A5
7
A4
8
STSOP
Top View
(not to scale)
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
16 GND
15 I/O2
14 I/O1
13 I/O0
12 A0
11 A1
10 A2
9 A3
A11
1
A9
2
A8
3
A13
4
WE
5
CE2
6
A15
7
VCC
8
NC
9
A16
10
A14
11
A12
12
A7
13
A6
14
A5
15
A4
16
TSOP I
Top View
(not to scale)
32 OE
31 A10
30 CE1
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
62128V-3
62128V-4
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 27, 2001
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