5962-9952302QZC(2003) Ver la hoja de datos (PDF) - Cypress Semiconductor

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5962-9952302QZC
(Rev.:2003)

5V, 3.3V, ISR™ High-Performance CPLDs

Cypress Semiconductor 

Ultra37000 CPLD Family

The buried macrocell also supports input register capability.

The buried macrocell can be configured to act as an input

register (D-type or latch) whose input comes from the I/O pin

associated with the neighboring macrocell. The output of all

buried macrocells is sent directly to the PIM regardless of its

configuration.

I/O Macrocell

Figure 2 illustrates the architecture of the I/O macrocell. The

I/O macrocell supports the same functions as the buried

macrocell with the addition of I/O capability. At the output of the

macrocell, a polarity control mux is available to select active

LOW or active HIGH signals. This has the added advantage

of allowing significant logic reduction to occur in many appli-

cations.

The Ultra37000 macrocell features a feedback path to the PIM

separate from the I/O pin input path. This means that if the

macrocell is buried (fed back internally only), the associated

I/O pin can still be used as an input.

Bus Hold Capabilities on all I/Os

Bus-hold, which is an improved version of the popular internal

pull-up resistor, is a weak latch connected to the pin that does

not degrade the device’s performance. As a latch, bus-hold

maintains the last state of a pin when the pin is placed in a

high-impedance state, thus reducing system noise in bus-

interface applications. Bus-hold additionally allows unused

device pins to remain unconnected on the board, which is

particularly useful during prototyping as designers can route

new signals to the device without cutting trace connections to

VCC or GND. For more information, see the application note

“Understanding Bus-Hold — A Feature of Cypress CPLDs.”

Programmable Slew Rate Control

Each output has a programmable configuration bit, which sets

the output slew rate to fast or slow. For designs concerned with

meeting FCC emissions standards the slow edge provides for

lower system noise. For designs requiring very high perfor-

mance the fast edge rate provides maximum system perfor-

mance.

Document #: 38-03007 Rev. *C

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