CY22801KSXC-XXX(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY22801KSXC-XXX Datasheet PDF : 23 Pages
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CY22801
Table 13. Clock Output Setting
CLKSRC2 CLKSRC1 CLKSRC0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Definition and Notes
Reference input.
DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are
4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8.
DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.
DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.
DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are
4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.
DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.
Reserved – do not use.
Table 14. Clock Output Register Setting
Address
D7
D6
D5
44H
1
1
1
45H CLKSRC0 for
1
1
CLKB
46H CLKSRC1 for CLKSRC0 for
1
CLKC
CLKC
D4
D3
D2
D1
D0
1
1
1
CLKSRC2 for CLKSRC1 for
CLKB
CLKB
1
CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for
CLKA
CLKA
CLKA
CLKC
1
1
1
1
1
Table 15. CLKOE Bit Setting
Address
D7
D6
D5
D4
D3
D2
D1
D0
09H
0
0
CLKC
CLKA
0
CLKB
0
0
Document #: 001-15571 Rev. *E
Page 10 of 23
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