CY22801KSXC-XXX(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY22801KSXC-XXX Datasheet PDF : 23 Pages
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CY22801
Table 8. Input Load Capacitor Register Bit Settings
Address
D7
D6
D5
13H
CapLoad(7) CapLoad(6) CapLoad(5)
D4
CapLoad(4)
D3
CapLoad(3)
D2
CapLoad(2)
D1
CapLoad(1)
D0
CapLoad(0)
Table 9. P Counter and Q Counter Register Definition
Address
40H
41H
42H
D7
1
PB(7)
PO
D6
1
PB(6)
Q(6)
D5
0
PB(5)
Q(5)
D4
Pump(2)
PB(4)
Q(4)
D3
Pump(1)
PB(3)
Q(3)
D2
Pump(0)
PB(2)
Q(2)
D1
PB(9)
PB(1)
Q(1)
D0
PB(8)
PB(0)
Q(0)
Table 10. PLL Post Divider Options
Address
0CH
47H
D7
DIV1SRC
DIV2SRC
D6
DIV1N(6)
DIV2N(6)
D5
DIV1N(5)
DIV2N(5)
D4
DIV1N(4)
DIV2N(4)
D3
DIV1N(3)
DIV2N(3)
D2
DIV1N(2)
DIV2N(2)
D1
DIV1N(1)
DIV2N(1)
D0
DIV1N(0)
DIV2N(0)
Table 11. Charge Pump Settings
Charge Pump Setting – Pump(2..0)
000
001
010
011
100
101, 110, 111
Calculated Ptotal
16 – 44
45 – 479
480 – 639
640 – 799
800 – 1023
Do not use – device will be unstable
Table 12. Register 40H Change Pump Bit Settings
Address
D7
D6
D5
40H
1
1
0
D4
Pump(2)
D3
Pump(1)
D2
Pump(0)
D1
PB(9)
D0
PB(8)
Although using the above table guarantees stability, it is recom-
mended to use the Print preview function in CyClocksRT to
determine the correct charge pump settings for optimal jitter
performance.
PLL stability cannot be guaranteed for values below 16 and
above 1023. If values above 1023 are needed, use CyClocksRT
to determine the best charge pump setting. To configure device
using serial interface, please refer CyClocksRT.
Clock Output Settings: CLKSRC – Clock Output
Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)],
[46H(7..6)]
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint switch
matrix defines which source is attached to each individual clock
output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H.
The remainder of register 46H(5:0) must be written with the
values stated in the register table when writing register values
46H(7:6).
When DIV1N is divisible by four, then CLKSRC(0,1,0) is
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1).
When DIV2N is divisible by four, then CLKSRC(1,0,1) is
guaranteed to be rising edge phase-aligned with
CLKSRC(1,0,0). When DIV2N is divisible by eight, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
CLKOE – Clock Output Enable Control [09H(5..0)]
Each clock output has its own output enable, controlled by
register 09H(5..0). To enable an output, set the corresponding
CLKOE bit to 1. CLKOE settings are in Table 15 on page 10.
Test, Reserved, and Blank Registers
Writing to any of the following registers causes the part to exhibit
abnormal behavior, as follows.
[00H to 08H]
[0AH to 0BH]
[0DH to 11H]
[14H to 3FH]
[43H]
[48H to FFH]
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved.
Document #: 001-15571 Rev. *E
Page 9 of 23
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