CY22800 Ver la hoja de datos (PDF) - Cypress Semiconductor
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Fabricante
CY22800 Datasheet PDF : 8 Pages
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CY22800
DC Electrical Specifications
Parameter
IOH
IOL
CIN1
CIN2
IIH
IIL
f∆XO
VVCXO
VIH
VIL
Name
Output High Current
Output Low Current
Input Capacitance
Input Capacitance
Input High Current
Input Low Current
VCXO Pullability Range
VCXO Input Range
Input High Voltage
Input Low Voltage
Description
VOH = VDD – 0.5, VDD = 3.3V (source)
VOL = 0.5, VDD = 3.3V (sink)
All input pins except XIN and XOUT
XIN and XOUT pins
VIH = VDD
VIL = 0V
CMOS levels, 70% of VDD
CMOS levels, 30% of VDD
Min.
12
12
–
–
–
–
±150
0
0.7
–
Typ.
24
24
–
24
5
–
–
–
–
–
Max.
–
–
7
–
10
50
VDD
–
0.3
Unit
mA
mA
pF
pF
µA
µA
ppm
V
VDD
VDD
AC Electrical Characteristics (VDD = 3.3V)
Parameter
Name
Description
Min.
DC
Output Duty Cycle
Duty Cycle is defined in Figure 3, 50% of VDD 45
t3
Rising Edge Slew Rate
Output Clock Rise Time, 20% - 80% of VDD
0.8
t4
Falling Edge Slew Rate
Output Clock Fall Time, 80% - 20% of VDD
0.8
t10
PLL Lock Time
–
Typ. Max. Unit
50 55 %
1.4 – V/ns
1.4 – V/ns
–
3 ms
Test Circuit
Figure 2. Test Circuit Diagram
VDD
0.1 µF
OUTPUTS
CLKout
CLOAD
Figure 4. Rise and Fall Time Definitions
t3
t4
80%
CLK
20%
GND
Figure 3. Duty Cycle Definition; DC = t2/t1
t1
t2
CLK
50%
50%
Document #: 001-07704 Rev. **
Page 6 of 8
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