CY22388 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY22388 Datasheet PDF : 10 Pages
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CY22388/89/91
CLKC and CLKE have related frequencies. Related
frequencies come from the same PLL but can have different
divider values.
In order to minimize PPM (Parts Per Million) error on the clock
outputs, a user should choose a crystal reference frequency
that is a common multiple of the desired PLL frequencies.
While this would be the ideal situation, this is not always the
case and the PLLs have high-resolution counters internally to
help minimize frequency deviation from the desired frequency.
PLL VCO frequencies are generated by the following
equation: FVCO = FREF * (P / Q)
Where FREF is the reference input frequency, P is the PLL
feedback divider and Q is the reference input divider.
A PLL is a feedback system where the VCO frequency divided
by P and reference frequency divided by Q are constantly
being compared and the VCO frequency is adjusted to achieve
a locked state. Figure 1 is a simplified drawing of a PLL.
Figure 1.
FR E F
/Q
V C O a nd
O th e r
c o m p o n e n ts
F VCO
/P
Frequency Select Pin Operation
Table 1. CY22388 16-pin TSSOP
Output Signal
CLOCK A
CLOCK B
CLOCK C & CLOCK D
CLOCK E
Frequency Selection
Lines
S2S1S0
S1S0
S0
FIXED
Table 2. CY22389 20-pin TSSOP
Output Signal
Frequency Selection
Lines
CLOCK A
S2S1S0
CLOCK B & CLOCK C
S1S0
CLOCK D, CLOCK E, & CLOCK F S0
CLOCK G
FIXED
CLOCK H
COPY OF CLOCK D
Table 3. CY22391 32-pin QFN
Output Signal
Frequency Selection
Lines
CLOCK A
S2S1S0
CLOCK B & CLOCK C
S1S0
CLOCK D, CLOCK E, & CLOCK F S0
CLOCK G
FIXED
CLOCK H
COPY OF CLOCK D
Document #: 38-07734 Rev. *B
Page 3 of 10
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