CY22150ZC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY22150ZC
Cypress Semiconductor
CY22150ZC Datasheet PDF : 13 Pages
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CY22150
Table 14. Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
VDD
VDDL
TS
TJ
Supply Voltage
I/O Supply Voltage
Storage Temperature[2]
Junction Temperature
Package Power Dissipation – Commercial Temp
–0.5
7.0
V
–0.5
7.0
V
–65
125
°C
125
°C
450
mW
Package Power Dissipation – Industrial Temp
380
mW
Digital Inputs
AVSS – 0.3 AVDD + 0.3
V
Digital Outputs referred to VDD
VSS – 0.3
VDD + 0.3
V
Digital Outputs referred to VDDL
VSS – 0.3
VDDL +0.3
V
ESD
Static Discharge Voltage per MIL-STD-833, Method 3015
2000
V
Table 15. Recommended Operating Conditions
Parameter
VDD
VDDLHI[3]
VDDLLO[3]
TAC
TAI
CLOAD
CLOAD
fREFD
fREFC
tPU
Description
Operating Voltage
Operating Voltage
Operating Voltage
Ambient Commercial Temp
Ambient Industrial Temp
Max. Load Capacitance, VDD/VDDL = 3.3V
Max. Load Capacitance, VDDL = 2.5V
Driven REF
Crystal REF
Power-up time for all VDDs to reach minimum
specified voltage (power ramps must be
monotonic)
Min.
3.135
3.135
2.375
0
–40
1
8
0.05
Typ.
3.3
3.3
2.5
Max.
3.465
3.465
2.625
70
85
15
15
133
30
500
Unit
V
V
V
°C
°C
pF
pF
MHz
MHz
ms
Table 16. DC Electrical Characteristics
Parameter[4]
Name
Description
Min.
Typ. Max.
Unit
IOH3.3
Output High Current VOH = VDD – 0.5, VDD/VDDL = 3.3V (sink) 12
24
mA
IOL3.3
Output Low Current VOL = 0.5, VDD/VDDL = 3.3V (source)
12
24
mA
IOH2.5
Output High Current VOH = VDDL – 0.5, VDDL = 2.5V (source)
8
16
mA
IOL2.5
Output Low Current VOL = 0.5, VDDL = 2.5V (sink)
8
16
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
0.3
VDD
CIN
Input Capacitance
SCLK and SDAT Pins
7
pF
IIZ
Input Leakage Current SCLK and SDAT Pins
5
µA
VHYS
Hysteresis of Schmitt SCLK and SDAT Pins
0.05
VDD
triggered inputs
IVDD[5,6]
IVDDL3.3[5,6]
IVDDL2.5[5,6]
Supply Current
Supply Current
Supply Current
AVDD/VDD Current
VDDL Current (VDDL = 3.465V)
VDDL Current (VDDL = 2.625V)
45
mA
25
mA
17
mA
Notes:
2. Rated for 10 years.
3. VDDLis only specified and characterized at 3.3V ± 5% and 2.5V ± 5%. VDDLmay be powered at any value between 3.465V and 2.375V.
4. Not 100% tested.
5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz.
6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations.
Document #: 38-07104 Rev. *F
Page 10 of 13
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