CY2213(2012) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY2213 Datasheet PDF : 16 Pages
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CY2213
State Transition Characteristics
Specifies the maximum settling time of the CLK and CLKB outputs from device power up. For VDD and VDDX any sequences are
allowed to power up and power down the CY2213.
From
To
Transition Latency
Description
VDD/VDDX On CLK/CLKB Normal
3 ms
Time from VDD/VDDX is applied and settled to CLK/CLKB outputs settled.
Functional Specifications
Crystal Input
The CY2213 receives its reference from an external crystal. Pin
XIN is the reference crystal input, and pin XOUT is the reference
crystal feedback. The parameters for the crystal are illustrated in
AC Device Characteristics on page 7. The oscillator circuit
requires external capacitors. Please refer to the application note
entitled Crystal Oscillator Topics for details.
Select Input
There is only one select input, pin S. This pin selects the
frequency multiplier in the PLL, and is a standard LVCMOS input.
The S pin has an internal pull up resistor. The multiplier selection
is illustrated in Frequency Table on page 3.
PECL Clock Output Driver
Figure 6 and Figure 7 show the Clock Output Driver.
PECL
Differential
Driver
Figure 6. Output Driving Load (-1)
VDD
Measurement Point
130
50
82
82
130
50
130
130
Measurement Point
PECL
Differential
Driver
Figure 7. Output Driving Load (-2)
62
45
Measurement Point
62
45
45
45
Measurement Point
Document Number: 38-07263 Rev. *H
Page 8 of 16
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