CY14B256Q3 Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY14B256Q3

256-Kbit (32 K × 8) Serial (SPI) nvSRAM

Cypress Semiconductor 

CY14B256Q1

CY14B256Q2

CY14B256Q3

SPI Modes

CY14B256Q1/CY14B256Q2/CY14B256Q3 may be driven by a

microcontroller with its SPI peripheral running in either of the

following two modes:

■ SPI Mode 0 (CPOL=0, CPHA=0)

■ SPI Mode 3 (CPOL=1, CPHA=1)

For both these modes, the input data is latched in on the rising

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles, is considered. The output data

is available on the falling edge of SCK.

The two SPI modes are shown in Figure 3 and Figure 4. The

status of clock when the bus master is in standby mode and not

transferring data is:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for the

either Mode 0 or Mode 3. The device detects the SPI mode from

the status of SCK pin when the device is selected by bringing the

CS pin LOW. If SCK pin is LOW when the device is selected, SPI

Mode 0 is assumed and if SCK pin is HIGH, it works in

SPI Mode 3.

Figure 3. SPI Mode 0

CS

SCK

012 345 67

SI

7 654321 0

MSB

LSB

Figure 4. SPI Mode 3

CS

SCK

012 34567

SI

7 654321 0

MSB

LSB

Document Number: 001-53882 Rev. *E

Page 7 of 26

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