CY14B256KA-SP45XIT Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B256KA-SP45XIT Datasheet PDF : 27 Pages
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CY14B256KA
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B45 AutoStore Disable
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation.
To initiate the AutoStore enable sequence, the following
sequence of CE or OE controlled read operations must be
performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) issued to save the
AutoStore state through subsequent power-down cycles. The
part comes from the factory with AutoStore enabled and 0x00
written in all cells.
Data Protection
The CY14B256KA protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and write operations. The low voltage condition is detected when
VCC is less than VSWITCH. If the CY14B256KA is in a write mode
(both CE and WE are LOW) at power-up, after a RECALL or
STORE, the write is inhibited until the SRAM is enabled after
tLZHSB (HSB to output active). This protects against inadvertent
writes during power-up or brown out conditions.
Real Time Clock Operation
nvTIME Operation
The CY14B256KA offers internal registers that contain clock,
alarm, watchdog, interrupt, and control functions. RTC registers
use the last 16 address locations of the SRAM. Internal double
buffering of the clock and timer information registers prevents
accessing transitional internal clock data during a read or write
operation. Double buffering also circumvents disrupting normal
timing counts or the clock accuracy of the internal clock when
accessing clock data. Clock and alarm registers store data in
BCD format.
RTC functionality is described in the following sections. The RTC
register addresses for CY14B256KA range from 0x7FF0 to
0x7FFF. Refer to Table 3 on page 11 and Table 4 on page 12 for
a detailed Register Map description.
Clock Operations
The clock registers maintain time up to 9,999 years in
one-second increments. The time can be set to any calendar
time and the clock automatically keeps track of days of the week
and month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time with a read cycle. These
registers contain the time of day in BCD format. Bits defined as
‘0’ are currently not used and are reserved for future use by
Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. Internal updates to the
CY14B256KA time keeping registers are stopped when the read
bit ‘R’ (in the flags register at 0x7FF0) is set to ‘1’ before reading
clock data to prevent reading of data in transition. Stopping the
register updates does not affect clock accuracy.
When a read sequence of RTC device is initiated, the update of
the user timekeeping registers stops and does not restart until a
‘0’ is written to the read bit ‘R’ (in the flags register at 0x7FF0).
After the end of read sequence, all the RTC registers are simul-
taneously updated within 20 ms.
Setting the Clock
A write access to the RTC device stops updates to the time
keeping registers and enables the time to be set when the write
bit ‘W’ (in the flags register at 0x7FF0) is set to ‘1’. The correct
day, date, and time is then written into the registers and must be
in 24 hour BCD format. The time written is referred to as the
“Base Time”. This value is stored in nonvolatile registers and
used in the calculation of the current time. When the write bit ‘W’
is cleared by writing ‘0’ to it, the values of timekeeping registers
are transferred to the actual clock counters after which the clock
resumes normal operation.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue
counting to 0xF before rolling over to 0x0 after which RTC
resumes normal operation.
Note After ‘W’ bit is set to ‘0’, values written into the timekeeping,
alarm, calibration, and interrupt registers are transferred to the
RTC time keeping counters in tRTCp time. These counter values
must be saved to nonvolatile memory either by initiating a
Software/Hardware STORE or AutoStore operation. While
working in AutoStore disabled mode, perform a STORE
operation after tRTCp time while writing into the RTC registers for
the modifications to be correctly recorded.
Backup Power
The RTC in the CY14B256KA is intended for permanently
powered operation. The VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When the primary power, VCC, fails and drops below
VSWITCH the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
Document Number: 001-55720 Rev. *G
Page 7 of 27
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