CY14C101Q2A-S104XI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14C101Q2A-S104XI Datasheet PDF : 34 Pages
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CY14C101Q
CY14B101Q, CY14E101Q
Device Operation
CY14X101Q is a 1-Mbit serial (SPI) nvSRAM memory with a
nonvolatile element in each memory cell. All the reads and writes
to nvSRAM happen to the SRAM, which gives nvSRAM the
unique capability to handle infinite writes to the memory. The
data in SRAM is secured by a STORE sequence which transfers
the data in parallel to the nonvolatile QuantumTrap cells. A small
capacitor (VCAP) is used to AutoStore the SRAM data in
nonvolatile cells when power goes down providing power-down
data security. The QuantumTrap nonvolatile elements built in the
reliable SONOS technology make nvSRAM the ideal choice for
secure data storage.
The 1-Mbit memory array is organized as 128 K words × 8 bits.
The memory can be accessed through a standard SPI interface
that enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This nvSRAM chip also supports
104 MHz SPI access speed with a special instruction for read
operation. This device supports SPI modes 0 and 3 (CPOL,
CPHA = 0, 0 and 1, 1) and operates as SPI slave. The device is
enabled using the Chip Select (CS) pin and accessed through
Serial Input (SI), Serial Output (SO), and Serial Clock (SCK)
pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the Status Register. Further,
the HOLD pin is used to suspend any serial communication
without resetting the serial sequence.
CY14X101Q uses the standard SPI opcodes for memory
access. In addition to the general SPI instructions for read and
write, it provides four special instructions that allow access to
four nvSRAM specific functions: STORE, RECALL, AutoStore
Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable you to choose a part which fits in best in their application.
The feature summary is given in Table 1.
Table 1. Feature Summary
Feature CY14X101Q1A CY14X101Q2A CY14X101Q3A
WP
Yes
No
Yes
VCAP
No
Yes
Yes
HSB
No
No
Yes
AutoStore
No
Yes
Yes
Power-Up
Yes
Yes
Yes
RECALL
Hardware
No
No
Yes
STORE
Software
Yes
Yes
Yes
STORE
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
allows you to perform infinite write operations. A write cycle is
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, three bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x00000 and the device continues to write.
The SPI write cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed. The data is read
out with zero cycle delay after the READ instruction is executed.
READ instruction can be used upto 40 MHz clock speed. The
READ instruction is issued through the SI pin of the nvSRAM and
consists of the READ opcode and three bytes of address. The
data is read out on the SO pin.
A speed higher than 40 MHz (up to 104 MHz) requires
FAST_READ instruction. The FAST_READ instruction is issued
through the SI pin of the nvSRAM and consists of the
FAST_READ opcode, three bytes of address, and one dummy
byte. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x00000 and the device continues to read.
The SPI read cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
Document #: 001-54393 Rev. *F
Page 4 of 34
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