CY14B104NA-BA25IT Ver la hoja de datos (PDF) - Cypress Semiconductor

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Fabricante

CY14B104NA-BA25IT

4-Mbit (512 K × 8/256 K × 16) nvSRAM

Cypress Semiconductor 

CY14B104LA, CY14B104NA

Software Controlled STORE/RECALL Cycle

Over the Operating Range

Parameter [42, 43]

Description

tRC

tSA

tCW

tHA

tRECALL

STORE/RECALL initiation cycle time

Address setup time

Clock pulse width

Address hold time

RECALL duration

20 ns

Min

Max

20

–

0

–

15

–

0

–

–

200

25 ns

Min

Max

25

–

0

–

20

–

0

–

–

200

Switching Waveforms – Software Controlled STORE/RECALL Cycle

Figure 12. CE and OE Controlled Software STORE/RECALL Cycle [43]

tRC

tRC

Address

Address #1

tSA

tCW

Address #6

tCW

CE

tSA

OE

tHA

tHA

tHA

tHA

HSB (STORE only)

DQ (DATA)

tLZCE

tHZCE

t DELAY

44

Note

High Impedance

tSTORE/tRECALL

45 ns

Min

Max

Unit

45

–

ns

0

–

ns

30

–

ns

0

–

ns

–

200 s

tHHHD

tLZHSB

RWI

Address

Figure 13. AutoStore Enable/Disable Cycle[43]

tRC

tRC

Address #1

tSA

tCW

Address #6

tCW

CE

tSA

OE

DQ (DATA)

tLZCE

tHA

tHA

tHZCE

tHA

tHA

44

Note

tSS

t DELAY

RWI

Notes

42. The software sequence is clocked with CE controlled or OE controlled reads.

43. The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE must be HIGH during all six consecutive cycles.

44. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.

Document Number: 001-49918 Rev. *L

Page 15 of 26

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