CY14B104NA-BA25IT Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY14B104NA-BA25IT

4-Mbit (512 K × 8/256 K × 16) nvSRAM

Cypress Semiconductor 

CY14B104LA, CY14B104NA

Switching Waveforms (continued)

Figure 7. SRAM Read Cycle #2 (CE and OE Controlled) [27, 28, 29]

Address

CE

OE

BHE, BLE

Data Output

High Impedance

ICC

Standby

Address Valid

tRC

tACE

tAA

tLZCE

tLZOE

tDOE

tDBE

tLZBE

tPU

Active

tHZCE

tHZOE

tHZBE

Output Data Valid

tPD

Address

CE

BHE, BLE

WE

Data Input

Data Output

Figure 8. SRAM Write Cycle #1 (WE Controlled) [27, 29, 30, 31]

tWC

Address Valid

tSCE

tHA

tSA

Previous Data

tBW

tAW

tPWE

tHZWE

tSD

tHD

Input Data Valid

tLZWE

High Impedance

Notes

27. BHE and BLE are applicable for × 16 configuration only.

28. WE must be HIGH during SRAM read cycles.

29. HSB must remain HIGH during read and write cycles.

30. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.

31. CE or WE must be >VIH during address transitions.

Document Number: 001-49918 Rev. *L

Page 12 of 26

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