CY14B104LA-ZS25XI(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

CY14B104LA-ZS25XI
(Rev.:2011)

4-Mbit (512 K × 8/256 K × 16) nvSRAM

Cypress Semiconductor 

CY14B104LA, CY14B104NA

Hardware STORE Cycle

Parameter

Description

tDHSB

tPHSB

tSS [38, 39]

HSB to output active time when write latch not set

Hardware STORE pulse width

Soft sequence processing time

20 ns

Min Max

–

20

15

–

–

100

25 ns

Min Max

–

25

15

–

–

100

Switching Waveforms

Figure 14. Hardware STORE Cycle[40]

45 ns

Unit

Min Max

–

25 ns

15

–

ns

–

100 μs

Write latch set

HSB (IN)

tPHSB

HSB (OUT)

tDELAY

DQ (Data Out)

tSTORE

tHHHD

tLZHSB

RWI

Write latch not set

tPHSB

HSB (IN)

HSB (OUT)

RWI

tDELAY

tDHSB

tDHSB

HSB pin is driven high to VCC only by Internal

100 kOhm resistor,

HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven low.

Figure 15. Soft Sequence Processing[38, 39]

Address

CE

VCC

Soft Sequence

tSS

Command

Address #1

tSA

Address #6

tCW

Soft Sequence

tSS

Command

Address #1

Address #6

tCW

Notes

38. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

39. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.

40. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

Document #: 001-49918 Rev. *H

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