CY14B104LA-ZS25XI(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY14B104LA-ZS25XI
(Rev.:2011)

4-Mbit (512 K × 8/256 K × 16) nvSRAM

Cypress Semiconductor 

CY14B104LA, CY14B104NA

AutoStore/Power-Up RECALL

Parameter

Description

tHRECALL [30] Power-Up RECALL duration

tSTORE [31] STORE cycle duration

tDELAY [32] Time allowed to complete SRAM write cycle

VSWITCH Low voltage trigger level

tVCCRISE[14] VCC rise time

VHDIS[14] HSB output disable voltage

tLZHSB[14] HSB to output active time

tHHHD[14] HSB high active time

20 ns

Min

Max

–

20

–

8

–

20

–

2.65

150

–

–

1.9

–

5

–

500

25 ns

Min

Max

–

20

–

8

–

25

–

2.65

150

–

–

1.9

–

5

–

500

Switching Waveforms

Figure 11. AutoStore or Power-Up RECALL[33]

45 ns

Unit

Min

Max

–

20

ms

–

8

ms

–

25

ns

–

2.65 V

150

–

μs

–

1.9

V

–

5

μs

–

500 ns

VCC

VSWITCH

VHDIS

HSB OUT

AutoStore

POWER-

UP

RECALL

Read & Write

Inhibited

(RWI)

tVCCRISE

34

Note

tHHHD

Note 31

tSTORE

tLZHSB

tHRECALL

tDELAY

tHHHD

Note31 tSTORE

Note34

tDELAY

tLZHSB

tHRECALL

POWER-UP

RECALL

Read & Write

BROWN POWER-UP

OUT

RECALL

AutoStore

Read & Write

POWER

DOWN

AutoStore

Notes

30. tHRECALL starts from the time VCC rises above VSWITCH.

31. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

32. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.

33. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.

34. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.

Document #: 001-49918 Rev. *H

Page 14 of 24

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