CY14B104LA-BA45XI(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

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Fabricante

CY14B104LA-BA45XI
(Rev.:2011)

4-Mbit (512 K × 8/256 K × 16) nvSRAM

Cypress Semiconductor 

CY14B104LA, CY14B104NA

Software Controlled STORE/RECALL Cycle

In the following table, the software controlled STORE and RECALL cycle parameters are listed.[35, 36]

Parameter

Description

tRC

tSA

tCW

tHA

tRECALL

STORE/RECALL initiation cycle time

Address setup time

Clock pulse width

Address hold time

RECALL duration

20 ns

25 ns

45 ns

Unit

Min Max Min Max Min Max

20

–

25

–

45

–

ns

0

–

0

–

0

–

ns

15

–

20

–

30

–

ns

0

–

0

–

0

–

ns

–

200

–

200

–

200

μs

Switching Waveforms

Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[36]

Address

tRC

Address #1

tSA

tCW

tRC

Address #6

tCW

CE

tSA

OE

HSB (STORE only)

DQ (DATA)

tLZCE

tHA

tHA

tHZCE

tHA

tHA

t DELAY

37

Note

High Impedance

tSTORE/tRECALL

tHHHD

tLZHSB

RWI

Figure 13. AutoStore Enable/Disable Cycle

Address

CE

tSA

tRC

Address #1

tSA

tCW

OE

DQ (DATA)

tLZCE

tHA

tHA

tHZCE

tRC

Address #6

tCW

tHA

tHA

37

Note

tSS

t DELAY

Notes

35. The software sequence is clocked with CE controlled or OE controlled reads.

36. The six consecutive addresses must be read in the order listed in Table 2 on page 6. WE must be HIGH during all six consecutive cycles.

37. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.

Document #: 001-49918 Rev. *H

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