CY14B104LA-BA45XI(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY14B104LA-BA45XI
(Rev.:2011)

4-Mbit (512 K × 8/256 K × 16) nvSRAM

Cypress Semiconductor 

CY14B104LA, CY14B104NA

Address

CE

BHE, BLE

WE

Data Input

Data Output

Figure 9. SRAM Write Cycle #2: CE Controlled[26, 27, 28, 29]

tWC

Address Valid

tSA

tSCE

tHA

tBW

tPWE

tSD

tHD

Input Data Valid

High Impedance

Address

CE

BHE, BLE

WE

Data Input

Data Output

Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[26, 27, 28, 29]

tWC

Address Valid

tSCE

tSA

tBW

tHA

tAW

tPWE

tSD

tHD

Input Data Valid

High Impedance

Notes

26. BHE and BLE are applicable for ×16 configuration only.

27. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.

28. HSB must remain HIGH during read and write cycles.

29. CE or WE must be >VIH during address transitions.

Document #: 001-49918 Rev. *H

Page 13 of 24

[+] Feedback

Share Link: