CY14B104K Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B104K Datasheet PDF : 29 Pages
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PRELIMINARY
CY14B104K/CY14B104M
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Figure 3. Watchdog Timer Block Diagram
Power Monitor
The CY14B104K/CY14B104M provides a power management
scheme with power fail interrupt capability. It also controls the
internal switch to backup power for the clock and protects the
memory from low VCC access. The power monitor is based on
an internal band gap reference circuit that compares the VCC
voltage to various thresholds.
As described in the section AutoStore Operation on page 3,
when VSWITCH is reached as VCC decays from power loss, a data
store operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor) to
operate the RTC oscillator.
When operating from the backup source, no data is read or
written and the clock functions are not available to the user. The
clock continues to operate in the background. The updated clock
data is available to the user after tHRECALL delay (see
AutoStore/Power Up RECALL on page 16) after VCC is restored
to the device.
Interrupts
The CY14B104K/CY14B104M provides three potential interrupt
sources. They include the watchdog timer, the power monitor,
and the clock or calendar alarm. Each are individually enabled
and assigned to drive the INT pin. In addition, each has an
associated flag bit that the host processor can use to determine
the cause of the interrupt. Some of the sources have additional
control bits that determine functional behavior. In addition, the
pin driver has three bits that specify its behavior when an
interrupt occurs.
The three interrupts each have a source and an enable. Both the
source and the enable must be active (true HIGH) to generate
an interrupt output. Only one source is necessary to drive the pin.
The user can identify the source by reading the flags or control
register, which contains the flags associated with each source.
All flags are cleared to ‘0’ when the register is read. The cycle
must be a complete read cycle (WE HIGH); otherwise, the flags
are not cleared. The power monitor has two programmable
settings that are explained in Power Monitor on page 8.
After an interrupt source is active, the pin driver determines the
behavior of the output. It has two programmable settings. Pin
driver control bits are located in the interrupt register.
According to the programming selections, the pin is driven in the
backup mode for an alarm interrupt. In addition, the pin is an
active LOW (open drain) or an active HIGH (push pull) driver. If
programmed for operation during backup mode, it is active LOW.
Lastly, the pin can provide a one shot function so that the active
condition is a pulse or a level condition. In one-shot mode, the
pulse width is internally fixed at approximately 200 ms. This
mode is intended to reset a host microcontroller. In the level
mode, the pin goes to its active polarity until the flags or control
register is read by the user. This mode is used as an interrupt to
a host microcontroller. The control bits are summarized as
follows.
Watchdog Interrupt Enable - WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog timeout occurs. When WIE is set to ‘0’, the watchdog
timer affects only the internal flag.
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When set to ‘0’, the alarm
match only affects the internal flag.
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When set to ‘0’,
the power fail monitor affects only the internal flag.
High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin can drive HIGH
only when VCC > VSWITCH. When set to ‘0’, the INT pin is active
LOW and the drive mode is open drain. Active LOW (open drain)
is operational even in battery backup mode.
Pulse/Level - P/L. When set to ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to
‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until
the flags or control register is read.
When an enabled interrupt source activates the INT pin, an
external host can read the flags or control register to determine
the cause. All flags are cleared when the register is read. If the
INT pin is programmed for level mode, then the condition clears
and the INT pin returns to its inactive state. If the pin is
programmed for pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the flags or control register is read. If the INT pin is
used as a host reset, then the flags or control register must not
be read during a reset.
During a power on reset with no battery, the interrupt register is
automatically loaded with the value 24h. This enables the power
fail interrupt with an active LOW pulse.
Document #: 001-07103 Rev. *I
Page 8 of 29
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