CY14B104M Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B104M Datasheet PDF : 29 Pages
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PRELIMINARY
CY14B104K/CY14B104M
If the voltage on the backup supply (VRTCcap or VRTCbat) falls
below their respective minimum level, the oscillator may fail,
leading to the oscillator failed condition which is detected when
system power is restored.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal, usually specified to 35 ppm limits at 25°C. This
error could equate to +1.53 minutes per month. The
CY14B104K/CY14B104M employs a calibration circuit that
improves the accuracy to +1/–2 ppm at 25°C. The calibration
circuit adds or subtracts counts from the oscillator divider circuit.
The number of times pulses are suppressed (subtracted,
negative calibration) or split (added, positive calibration)
depends on the value loaded into the five calibration bits found
in the calibration register at 0x1FFF8. Adding counts speeds the
clock up; subtracting counts slows the clock down. The
calibration bits occupy the five lower order bits in the control
register 8. These bits are set to represent any value between 0
and 31 in binary form. Bit D5 is a sign bit, where ‘1’ indicates
positive calibration and ‘0’ indicates negative calibration.
Calibration occurs within a 64 minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator cycles.
If a binary ‘1’ is loaded into the register, only the first 2 minutes
of the 64 minute cycle are modified; if a binary ‘6’ is loaded, the
first 12 are affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles
for every 125,829,120 actual oscillator cycles. That is 4.068 or
–2.034 ppm of adjustment for every calibration step in the
calibration register.
To determine how to set the calibration, the CAL bit in the flags
register at 0x1FFF0 is set to ‘1’, which causes the INT pin to
toggle at a nominal 512 Hz. Any deviation measured from the
512 Hz indicates the degree and direction of the required
correction. For example, a reading of 512.010124 Hz indicates
a +20 ppm error, which requires the loading of a –10 (001010)
into the calibration register. Note that setting or changing the
calibration register does not affect the frequency test output
frequency.
Alarm
The alarm function compares user programmed values with the
corresponding time of day values. When a match occurs, the
alarm event occurs. The alarm drives an internal flag, AF, and
may drive the INT pin if desired.
There are four alarm match fields. They are date, hours, minutes,
and seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process.
Depending on the match bits, the alarm can occur as specifically
as one particular second on one day of the month, or as
frequently as once per second continuously. The MSB of each
alarm register is a match bit. Selecting none of the match bits (all
1s) indicates that no match is required. The alarm occurs every
second. Setting the match select bit for seconds to ‘0’ causes the
logic to match the seconds alarm value to the current time of day.
Since a match occurs for only one value per minute, the alarm
occurs once per minute. Similarly, setting the seconds and
minutes match bits causes an exact match of these values. Thus,
an alarm occurs once per hour. Setting seconds, minutes, and
hours causes a match once per day. Lastly, selecting all match
values causes an exact time and date match. Selecting other bit
combinations does not produce meaningful results; however, the
alarm circuit must follow the functions described.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x1FFF0 indicates that a date or time match has occurred. The
AF bit is set to ‘1’ when a match occurs. Reading the flags or
control register clears the alarm flag bit (and all others). A
hardware interrupt pin may also be used to detect an alarm
event.
Watchdog Timer
The watchdog timer is a free running down counter that uses the
32 Hz clock (31.25 ms) derived from the crystal oscillator. The
oscillator must be running for the watchdog to function. It begins
counting down from the value loaded in the watchdog timer
register.
The counter consists of a loadable register and a free running
counter. On power up, the watchdog timeout value in register
0x1FFF7 is loaded into the counter load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of 0. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
The timeout interrupt is prevented by setting WDS bit to ‘1’ before
the counter reaches ‘0’. This causes the counter to reload with
the watchdog timeout value and get restarted. As long as the
WDS bit is set before the counter reaches the terminal value, the
interrupt and flag never occurs.
New timeout values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’ (from the previous operation), new
writes to the watchdog timeout value bits D5–D0 allow the modifi-
cation of timeout values. When WDW is ‘1’, then writes to bits
D5–D0 are ignored. The WDW function allows to set the WDS
bit without concern that the watchdog timer value is modified. A
logical diagram of the watchdog timer is shown in Figure 3 on
page 8. Note that setting the watchdog timeout value to ‘0’ is
otherwise meaningless and as a result, disables the watchdog
function.
The output of the watchdog timer is a flag bit WDF that is set if
the watchdog is allowed to timeout. The flag is set on a watchdog
timeout and cleared when the flags or control register is read by
the user. The user can also enable an optional interrupt source
to drive the INT pin if the watchdog timeout occurs.
Document #: 001-07103 Rev. *I
Page 7 of 29
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