CY14B104M Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B104M Datasheet PDF : 29 Pages
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PRELIMINARY
CY14B104K/CY14B104M
Data Protection
The CY14B104K/CY14B104M protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14B104K/CY14B104M
is in a write mode (both CE and WE LOW) at power up, after a
RECALL, or after a STORE, the write is inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer CY application note AN1064.
Real-Time-Clock Operation
nvTIME Operation
The CY14B104K/CY14B104M offers internal registers that
contain clock, alarm, watchdog, interrupt, and control functions.
Internal double buffering of the clock and the clock or timer
information registers prevents accessing transitional internal
clock data during a read or write operation. Double buffering also
circumvents disrupting normal timing counts or the clock
accuracy of the internal clock when accessing clock data. Clock
and alarm registers store data in BCD format.
Clock Operations
The clock registers maintain time up to 9,999 years in one
second increments. The time can be set to any calendar time and
the clock automatically keeps track of days of the week and
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
While the double buffered RTC register structure reduces the
chance of reading incorrect data from the clock, stop internal
updates to the CY14B104K/CY14B104M clock registers before
reading clock data, to prevent reading of data in transition.
Stopping the internal register updates does not affect clock
accuracy. The updating process is stopped by writing a ‘1’ to the
read bit ‘R’ (in the flags register at 0x1FFF0), and does not restart
until a ‘0’ is written to the read bit. The RTC registers are then
read while the internal clock continues to run. Within 20 ms after
a ‘0’ is written to the read bit, all CY14B104K/CY14B104M
registers are simultaneously updated.
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x1FFF0) to a ‘1’
stops updates to the CY14B104K/CY14B104M registers. The
correct day, date, and time is then written into the registers in 24
hour BCD format. The time written is referred to as the “Base
Time”. This value is stored in nonvolatile registers and used in
the calculation of the current time. Resetting the write bit to ‘0’
transfers those values to the actual clock counters, after which
the clock resumes normal operation.
Backup Power
The RTC in the CY14B104K/CY14B104M is intended for perma-
nently powered operation. The VRTCcap or VRTCbat pin is
connected depending on whether a capacitor or battery is
chosen for the application. When the primary power, VCC, fails
and drops below VSWITCH the device switches to the backup
power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14B104K/CY14B104M
consumes a maximum of 300 nanoamps at 2 volts. Capacitor or
battery values must be chosen according to the application.
Backup time values based on maximum current specifications
are shown in the following table. Nominal times are
approximately three times longer.
Table 2. RTC Backup Time
Capacitor Value
0.1F
0.47F
1.0F
Backup Time
72 hours
14 days
30 days
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3V lithium is recommended and the
CY14B104K/CY14B104M sources current only from the battery
when the primary power is removed. The battery is not, however,
recharged at any time by the CY14B104K/CY14B104M. The
battery capacity must be chosen for total anticipated cumulative
down time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x1FFF8 controls
the start and stop of the oscillator. This bit is nonvolatile and is
shipped to customers in the “enabled” (set to 0) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately 5 seconds (10 seconds maximum) for the
oscillator to start.
The CY14B104K/CY14B104M has the ability to detect oscillator
failure. This is recorded in the OSCF (Oscillator Failed bit) of the
flags register at the address 0x1FFF0. When the device is
powered on (VCC goes above VSWITCH) the OSCEN bit is
checked for “enabled” status. If the OSCEN bit is enabled and
the oscillator is not active, the OSCF bit is set. Check for this
condition and then write ‘0’ to clear the flag. Note that in addition
to setting the OSCF flag bit, the time registers are reset to the
“Base Time” (see Setting the Clock on page 6), which is the value
last written to the timekeeping registers. The control or
calibration registers and the OSCEN bit are not affected by the
‘oscillator failed’ condition.
Document #: 001-07103 Rev. *I
Page 6 of 29
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