CY14B101Q1-LHXI Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
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CY14B101Q1-LHXI Datasheet PDF : 27 Pages
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CY14B101Q1
CY14B101Q2
CY14B101Q3
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tristated.
Status Register
CY14B101Q1/CY14B101Q2/CY14B101Q3 has an 8-bit status
register. The bits in the status register are used to configure the
SPI bus. These bits are described in the Table 4 on page 10.
Figure 4. System Configuration Using SPI nvSRAM
SCK
MOSI
M IS O
uC ontroller
CS1
HOLD1
CS2
HOLD2
SCK SI
SO
CY14B101Qx
CS
HOLD
SCK SI
SO
CY14B101Qx
CS
HOLD
SPI Modes
CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a
microcontroller with its SPI peripheral running in either of the
following two modes:
â– SPI Mode 0 (CPOL=0, CPHA=0)
â– SPI Mode 3 (CPOL=1, CPHA=1)
For both these modes, the input data is latched-in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge, after the clock toggles, is considered. The output
data is available on the falling edge of SCK.
The two SPI modes are shown in Figure 5 and Figure 6. The
status of clock when the bus master is in standby mode and not
transferring data is:
â– SCK remains at 0 for Mode 0
â– SCK remains at 1 for Mode 3
CPOL and CPHA bits must be set in the SPI controller for the
either Mode 0 or Mode 3. The device detects the SPI mode from
the status of SCK pin when the device is selected by bringing the
CS pin LOW. If SCK pin is LOW when the device is selected, SPI
Mode 0 is assumed and if SCK pin is HIGH, it works in SPI
Mode 3.
Figure 5. SPI Mode 0
CS
SCK
012 345 67
SI
7 654321 0
MSB
LSB
Figure 6. SPI Mode 3
CS
SCK
012 34567
SI
7 654321 0
MSB
LSB
Document Number: 001-50091 Rev. *L
Page 8 of 27
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