CY14B101Q2-LHXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B101Q2-LHXI Datasheet PDF : 27 Pages
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CY14B101Q1
CY14B101Q2
CY14B101Q3
Device Operation
CY14B101Q1/CY14B101Q2/CY14B101Q3 is a 1-Mbit nvSRAM
memory with a nonvolatile element in each memory cell. All the
reads and writes to nvSRAM happen to the SRAM, which gives
nvSRAM the unique capability to handle infinite writes to the
memory. The data in SRAM is secured by a STORE sequence,
which transfers the data in parallel to the nonvolatile
QuantumTrap cells. A small capacitor (VCAP) is used to
AutoStore the SRAM data in nonvolatile cells when power goes
down providing power-down data security. The QuantumTrap
nonvolatile elements built in the reliable SONOS technology
make nvSRAM the ideal choice for secure data storage.
The 1 Mbit memory array is organized as 128 K words × 8 bits.
The memory is accessed through a standard SPI interface that
enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The device is enabled using the Chip Select (CS) pin and
accessed through Serial Input (SI), Serial Output (SO), and
Serial Clock (SCK) pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the status register. Further, the
HOLD pin can be used to suspend any serial communication
without resetting the serial sequence.
CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard
SPI opcodes for memory access. In addition to the general SPI
instructions for read and write, it provides four special
instructions which enable access to four nvSRAM specific
functions: STORE, RECALL, AutoStore Disable (ASDISB), and
AutoStore Enable (ASENB).
The major benefit of serial (SPI) nvSRAM over serial EEPROMs
is that all reads and writes to nvSRAM are performed at the
speed of SPI bus with zero cycle delay. Therefore, no wait time
is required after any of the memory accesses. The STORE and
RECALL operations need finite time to complete and all memory
accesses are inhibited during this time. While a STORE or
RECALL operation is in progress, the busy status of the device
is indicated by the Hardware STORE Busy (HSB) pin and also
reflected on the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable the user to choose a part which fits in best in their
application. The feature summary is given in Table 1.
Table 1. Feature Summary
Feature
WP
VCAP
HSB
AutoStore
Power Up
RECALL
Hardware
STORE
Software
STORE
CY14B101Q1
Yes
No
No
No
Yes
CY14B101Q2
No
Yes
No
Yes
Yes
CY14B101Q3
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables the user to perform infinite write operations. A write cycle
is performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, three bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the memory access
section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed and the data is
read out with zero cycle delay after the READ instruction is
executed. The READ instruction is issued through the SI pin of
the nvSRAM and consists of the READ opcode and 3 bytes of
address. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the memory access
section of SPI Protocol Description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device stores data to the
nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated,
read/write
to
CY14B101Q1/CY14B101Q2/CY14B101Q3 is inhibited until the
cycle is completed.
The HSB signal or the RDY bit in the Status register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
Document Number: 001-50091 Rev. *L
Page 5 of 27
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