CY14B101Q1-SFXIT Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B101Q1-SFXIT Datasheet PDF : 27 Pages
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CY14B101Q1
CY14B101Q2
CY14B101Q3
Pin Definitions
Pin Name I/O Type
Description
CS
Input Chip select. Activates the device when pulled LOW. Driving this pin high puts the device in low power
standby mode.
SCK
Input
Serial clock. Runs at speeds up to maximum of fSCK. Serial input is latched at the rising edge of this
clock. Serial output is driven at the falling edge of the clock.
SI
Input Serial input. Pin for input of all SPI instructions and data.
SO
Output Serial output. Pin for output of data through SPI.
WP
Input Write protect. Implements hardware write protection in SPI.
HOLD
Input HOLD pin. suspends serial operation.
HSB
Input/Output Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak
internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
NC
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM
to nonvolatile elements. If AutoStore is not needed, this pin must be left as No connect. It must never be
connected to VSS.
No connect No connect: This pin is not connected to the die.
VSS Power supply Ground
VCC Power supply Power supply (2.7 V to 3.6 V)
EXPOSED No connect The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. It is recommended
PAD
to connect the EXPOSED PAD to VSS. Thermal vias can be used to increase thermal conductivity.
Document Number: 001-50091 Rev. *L
Page 4 of 27
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