CY14B101Q2 Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY14B101Q2

1-Mbit (128 K × 8) Serial SPI nvSRAM

Cypress Semiconductor 

CY14B101Q1

CY14B101Q2

CY14B101Q3

Status Register

The status register bits are listed in Table 4. The status register consists of a Ready bit (RDY) and data protection bits BP1, BP0,

WEN, and WPEN. The RDY bit can be polled to check the Ready or Busy status while a nvSRAM STORE or Software RECALL cycle

is in progress. The status register can be modified by WRSR instruction and read by RDSR instruction. However, only the WPEN,

BP1, and BP0 bits of the Status Register can be modified by using WRSR instruction. The WRSR instruction has no effect on WEN

and RDY bits. The default value shipped from the factory for WEN, BP0, BP1, bits 4-6 and WPEN bits is ‘0’.

Table 3. Status Register Format

Bit 7

WPEN (0)

Bit 6

X (0)

Bit 5

X (0)

Bit 4

X (0)

Bit 3

BP1 (0)

Bit 2

BP0 (0)

Bit 1

WEN (0)

Bit 0

RDY

Table 4. Status Register Bit Definition

Bit

Bit 0 (RDY)

Bit 1 (WEN)

Bit 2 (BP0)

Bit 3 (BP1)

Bits 4-6

Bit 7 (WPEN)

Definition

Description

Ready

Read only bit indicates the ready status of device to perform a memory access. This bit is

set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.

Write Enable

WEN indicates if the device is Write Enabled. This bit defaults to ‘0’ (disabled) on power-up.

WEN = '1' --> Write Enabled

WEN = '0' --> Write Disabled

Block protect bit ‘0’ Used for block protection. For details see Table 5 on page 11.

Block protect bit ‘1’ Used for block protection. For details see Table 5 on page 11.

Don’t care

Bits are writable and volatile. On power-up, bits are written with ‘0’.

Write protect enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 6 on page 12.

Read Status Register (RDSR) Instruction

The RDSR instruction provides access to the status register.

This instruction is used to probe the Write Enable Status of the

device or the Ready status of the device. RDY bit is set by the

device to ‘1’ whenever a STORE or Software RECALL cycle is

in progress. The block protection and WPEN bits indicate the

extent of protection employed.

This instruction is issued after the falling edge of CS using the

opcode for RDSR.

Write Status Register (WRSR) Instruction

The WRSR instruction enables the user to write to the Status

register. However, this instruction cannot be used to modify bit 0

and bit 1 (RDY and WEN). The BP0 and BP1 bits can be used

to select one of four levels of block protection. Further, WPEN bit

must be set to ‘1’ to enable the use of write protect (WP) pin.

WRSR instruction is a write instruction and needs writes to be

enabled (WEN bit set to ‘1’) using the WREN instruction before

it is issued. The instruction is issued after the falling edge of CS

using the opcode for WRSR followed by 8 bits of data to be

stored in the Status Register. Since only bits 2, 3, and 7 can be

modified by WRSR instruction; therefore, it is recommended to

leave the bits 4-6 as ‘0’ while writing to the Status Register

Note In CY14B101Q1/CY14B101Q2/CY14B101Q3, the values

written to Status Register are saved to nonvolatile memory only

after a STORE operation. If AutoStore is disabled (or while using

CY14B101Q1), any modifications to the Status Register must be

secured by performing a Software STORE operation.

Note CY14B101Q2 does not have WP pin. Any modification to

bit 7 of the Status register has no effect on the functionality of

CY14B101Q2.

Figure 7. Read Status Register (RDSR) Instruction Timing

CS

SCK

0 1 2 3 4 5 67 01 2 3 4 5 67

SI

0 0 0 0 01 0 1 0

MSB

LSB

SO

HI-Z

D7 D6 D5 D4 D3 D2 D1 D0

MSB

Data

LSB

Document Number: 001-50091 Rev. *L

Page 10 of 27

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