CY14B101Q3-SFXC Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY14B101Q3-SFXC

1 Mbit (128K x 8) Serial SPI nvSRAM

Cypress Semiconductor 

PRELIMINARY

CY14B101Q1

CY14B101Q2

CY14B101Q3

Figure 4. System Configuration Using SPI nvSRAM

SCK

MOSI

M IS O

uC ontroller

CS1

HOLD1

CS2

HOLD2

SCK SI

SO

CY14B101Qx

CS

HOLD

SCK SI

SO

CY14B101Qx

CS

HOLD

SPI Modes

CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a

microcontroller with its SPI peripheral running in either of the

following two modes:

■ SPI Mode 0 (CPOL=0, CPHA=0)

■ SPI Mode 3 (CPOL=1, CPHA=1)

For both these modes, input data is latched-in on the rising edge

of Serial Clock (SCK) starting from the first rising edge after CS

goes active. If the clock starts from a HIGH state (in mode 3), the

first rising edge, after the clock toggles, is considered. The output

data is available on the falling edge of Serial Clock (SCK).

Figure 5. SPI Mode 0

CS

SCK

012 345 67

The two SPI modes are shown in Figure 5 and Figure 6. The

status of clock when the bus master is in Standby mode and not

transferring data is:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

CPOL and CPHA bits must be set in the SPI controller for either

Mode 0 or Mode 3. The device detects the SPI mode from the

status of SCK pin when the device is selected by bringing the CS

pin LOW. If SCK pin is LOW when device is selected, SPI Mode

0 is assumed and if SCK pin is HIGH, it works in SPI Mode 3.

Figure 6. SPI Mode 3

CS

SCK

012 34567

SI

7 654321 0

MSB

LSB

SI

7 654321 0

MSB

LSB

Document #: 001-50091 Rev. *B

Page 6 of 22

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