CY14B101P(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY14B101P
(Rev.:2011)

1-Mbit (128 K × 8) Automotive Serial (SPI) nvSRAM with Real Time Clock

Cypress Semiconductor 

PRELIMINARY

CY14B101P

Figure 2 shows the proper connection of the storage capacitor

(VCAP) for AutoStore operation. Refer to DC Electrical Charac-

teristics on page 24 for the size of the VCAP.

Figure 2. AutoStore Mode

VCC

0.1 uF

VCC

CS

VCAP

VSS

VCAP

Software STORE Operation

Software STORE allows the user to trigger a STORE operation

through a special SPI instruction. STORE operation is initiated

by executing STORE instruction irrespective of whether a write

has been performed since the last NV operation.

A STORE cycle takes tSTORE time to complete, during which all

the memory accesses to nvSRAM are inhibited. The RDY bit of

the Status Register or the HSB pin may be polled to find the

Ready/Busy status of the nvSRAM. After the tSTORE cycle time

is completed, the SRAM is activated again for read and write

operations.

Hardware STORE and HSB pin Operation

The HSB pin in CY14B101P is used to control and acknowledge

STORE operations. If no STORE/RECALL is in progress, this pin

can be used to request a Hardware STORE cycle. When the

HSB pin is driven LOW, the CY14B101P conditionally initiates a

STORE operation after tDELAY duration. An STORE cycle starts

only if a write to the SRAM has been performed since the last

STORE or RECALL cycle. Reads and Writes to the memory are

inhibited for tSTORE duration or as long as HSB pin is LOW.

The HSB pin also acts as an open drain driver (internal 100 kΩ

weak pull-up resistor) that is internally driven LOW to indicate a

busy condition when the STORE (initiated by any means) is in

progress.

Note After each Hardware and Software STORE operation HSB

is driven HIGH for a short time (tHHHD) with standard output high

current and then remains HIGH by internal 100 kΩ pull-up

resistor.

Note For successfull last data byte STORE, a hardware STORE

should be initiated atleast one clock cycle after the last data bit

D0 is recieved.

Upon completion of the STORE operation, the nvSRAM memory

access is inhibited for tLZHSB time after HSB pin returns HIGH.

Leave the HSB unconnected if it is not used.

RECALL Operation

A RECALL operation transfers the data stored in the nonvolatile

QuantumTrap elements to the SRAM. In CY14B101P, a

RECALL may be initiated in two ways: Hardware RECALL,

initiated on power-up; and Software RECALL, initiated by a SPI

RECALL instruction.

Internally, RECALL is a two step procedure. First, the SRAM data

is cleared. Next, the nonvolatile information is transferred into the

SRAM cells. All memory accesses are inhibited while a RECALL

cycle is in progress. The RECALL operation does not alter the

data in the nonvolatile elements.

Hardware RECALL (Power-Up)

During power-up, when VCC crosses VSWITCH, an automatic

RECALL sequence is initiated which transfers the content of

nonvolatile memory on to the SRAM.

A Power-Up RECALL cycle takes tFA time to complete and the

memory access is disabled during this time. HSB pin is used to

detect the Ready status of the device.

Software RECALL

Software RECALL allows the user to initiate a RECALL operation

to restore the content of nonvolatile memory on to the SRAM. In

CY14B101P, this can be done by issuing a RECALL instruction

in SPI.

A Software RECALL takes tRECALL time to complete during

which all memory accesses to nvSRAM are inhibited. The

controller must provide sufficient delay for the RECALL operation

to complete before issuing any memory access instructions.

Document #: 001-61932 Rev. *B

Page 5 of 35

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