CY14B101P(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY14B101P
(Rev.:2011)

1-Mbit (128 K × 8) Automotive Serial (SPI) nvSRAM with Real Time Clock

Cypress Semiconductor 

PRELIMINARY

CY14B101P

Device Operation

CY14B101P is a 1-Mbit nvSRAM memory with integrated RTC

and SPI interface. All the reads and writes to nvSRAM happen

to the SRAM which gives nvSRAM the unique capability to

handle infinite writes to the memory. The data in SRAM is

secured by a STORE sequence that transfers the data in parallel

to the nonvolatile QuantumTrap cells. A small capacitor (VCAP)

is used to AutoStore the SRAM data in nonvolatile cells when

power goes down providing power-down data security. The

QuantumTrap nonvolatile elements built in the reliable SONOS

technology make nvSRAM the ideal choice for secure data

storage.

In CY14B101P, the 1-Mbit memory array is organized as 128 K

words × 8 bits. The memory is accessed through a standard SPI

interface that enables very high clock speeds up to 40 MHz with

zero delay read and write cycles. CY14B101P supports SPI

modes 0 and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as

SPI slave. The device is enabled using the Chip Select (CS) pin

and accessed through serial input (SI), serial output (SO), and

serial clock (SCK) pins.

CY14B101P provides the feature for hardware and software

write protection through WP pin and WRDI instruction.

CY14B101P also provides mechanisms for block write

protection (one quarter, one-half, or full array) using BP0 and

BP1 pins in the Status Register. Further, the HOLD pin is used

to suspend any serial communication without resetting the serial

sequence.

CY14B101P uses the standard SPI opcodes for memory access.

In addition to the general SPI instructions for read and write,

CY14B101P provides two special instructions that enable

access to two nvSRAM specific functions: STORE and RECALL.

The major benefit of serial (SPI) nvSRAM over serial EEPROMs

is that all reads and writes to nvSRAM are performed at the

speed of SPI bus with zero cycle delay. Therefore, no wait time

is required after any of the memory accesses. The STORE and

RECALL operations need finite time to complete and all memory

accesses are inhibited during this time. While a STORE or

RECALL operation is in progress, the busy status of the device

is indicated by the Hardware STORE Busy (HSB) pin and also

reflected on the RDY bit of the Status Register.

SRAM Write

All writes to nvSRAM are carried out on the SRAM and do not

use up any endurance cycles of the nonvolatile memory. This

enables the user to perform infinite write operations. A write cycle

is performed through the WRITE instruction. The WRITE

instruction is issued through the SI pin of the nvSRAM and

consists of the WRITE opcode, 3 bytes of address, and 1 byte of

data. Write to nvSRAM is done at SPI bus speed with zero cycle

delay.

CY14B101P allows burst mode writes to be performed through

SPI. This enables write operations on consecutive addresses

without issuing a new WRITE instruction. When the last address

in memory is reached in burst mode, the address rolls over to

0x0000 and the device continues to write.

The SPI write cycle sequence is defined in the Memory Access

section of SPI Protocol Description.

SRAM Read

A read cycle in CY14B101P is performed at the SPI bus speed

and the data is read out with zero cycle delay after the READ

instruction is executed. The READ instruction is issued through

the SI pin of the nvSRAM and consists of the READ opcode and

three bytes of address. The data is read out on the SO pin.

CY14B101P enables burst mode reads to be performed through

SPI. This enables reads on consecutive addresses without

issuing a new READ instruction. When the last address in

memory is reached in burst mode read, the address rolls over to

0x0000 and the device continues to read.

The SPI read cycle sequence is defined in the Memory Access

section of SPI Protocol Description

STORE Operation

STORE operation transfers the data from the SRAM to the

nonvolatile QuantumTrap cells. The CY14B101P stores data to

the nonvolatile cells using one of the three STORE operations:

AutoStore, activated on device power-down; Software STORE,

activated by a STORE instruction; and Hardware STORE,

activated by the HSB. During the STORE cycle, an erase of the

previous nonvolatile data is first performed, followed by a

program of the nonvolatile elements. After a STORE cycle is

initiated, read/write to CY14B101P is inhibited until the cycle is

completed.

The HSB signal or the RDY bit in the Status Register can be

monitored by the system to detect if a STORE or Software

RECALL cycle is in progress. The busy status of nvSRAM is

indicated by HSB being pulled LOW or RDY bit being set to ‘1’.

To avoid unnecessary nonvolatile STOREs, Hardware STORE

operation is ignored unless at least one write operation has taken

place since the most recent STORE or RECALL cycle. However,

software initiated STORE cycles are performed regardless of

whether a write operation has taken place.

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM which

automatically stores the SRAM data to QuantumTrap during

power-down. This STORE makes use of an external capacitor

(VCAP) which enables the device to safely STORE the data in the

nonvolatile memory when power goes down.

During normal operation, the device draws current from VCC to

charge the capacitor connected to the VCAP pin. When the

voltage on the VCC pin drops below VSWITCH during power-down,

the device inhibits all memory accesses to nvSRAM and

automatically performs a STORE operation using the charge

from the VCAP capacitor.

Note The nvSRAM should not be powered down without the

specified capacitor on VCAP pin. Without proper VCAP, the

AutoStore operation will corrupt the nvSRAM and make the part

nonfunctional.

Document #: 001-61932 Rev. *B

Page 4 of 35

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