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CY14B101P(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY14B101P Datasheet PDF : 35 Pages
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PRELIMINARY
CY14B101P
1-Mbit (128 K × 8) Automotive Serial (SPI)
nvSRAM with Real Time Clock
1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock
Features
1 Mbit nonvolatile static random access memory (nvSRAM)
Internally organized as 128 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by the user
using HSB pin (hardware STORE) or SPI instruction
(Software STORE)
RECALL to SRAM initiated on power-up (power-up RECALL)
or by SPI instruction (software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
STORE cycles to QuantumTrap
• Automotive-A: 1,000 K STORE cycles
• Automotive-E: 100 K STORE cycles
Data retention
• Automotive-A: 20 years
• Automotive-E: 2 years
Real time clock
Full-featured real time clock
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Backup current of 0.35 uA (typ)
High-speed serial peripheral interface (SPI)
40 MHz clock rate - SRAM memory access
25 MHz clock rate - RTC memory access
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Logic Block Diagram
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using the Write Disable Instruction
Software block protection for one-quarter, one-half, or entire
array
Low power consumption
Operating voltages:
• Automotive-A: VCC = 2.7 V to 3.6 V
• Automotive-E: VCC = 3.0 V to 3.6 V
Average active current of 10 mA at 40 MHz operation
Industry standard configurations
Temperature ranges
• Automotive-A: –40 °C to +85 °C
• Automotive-E: –40 °C to +125 °C
16-pin small outline integrated circuit (SOIC) package
Pb-free and restriction of hazardous substances (RoHS)
compliant
Overview
The Cypress CY14B101P combines a 1 Mbit nonvolatile static
RAM with full-featured real time clock in a monolithic integrated
circuit with serial SPI interface. The memory is organized as
128 K words of 8 bits each. The embedded nonvolatile elements
incorporate the QuantumTrap technology, creating the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while the QuantumTrap cells provide
highly reliable nonvolatile storage of data. Data transfers from
SRAM to the nonvolatile elements (STORE operation) takes
place automatically at power-down. On power-up, data is
restored to the SRAM from the nonvolatile memory (RECALL
operation). The STORE and RECALL operations can also be
initiated by the user through SPI instruction.
VCC
VCAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
128 K X 8
SRAM Array
128 K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
HSB
Instruction
register
D0-D7
Address
Decoder
A0-A16
RTC
Xout
X in
INT
SI
Data I/O register
MUX
SO
Status Register
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-61932 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 22, 2011

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