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CY14B101P-SFXIT
(Rev.:2012)

1-Mbit (128 K × 8) Serial SPI nvSRAM with Real Time Clock

Cypress Semiconductor 

CY14B101P

Write Disable (WRDI) Instruction

Write Disable instruction disables the write by clearing the WEN

bit to ‘0’ in order to protect the device against inadvertent writes.

This instruction is issued following the falling edge of CS followed

by opcode for WRDI instruction. The WEN bit is cleared on the

rising edge of CS following a WRDI instruction.

Figure 9. WRDI Instruction

CS

SCK

01 234567

SI

00000100

SO

HI-Z

Block Protection

Block protection is provided using the BP0 and BP1 pins of the

Status Register. These bits can be set using WRSR instruction

and probed using the RDSR instruction. The nvSRAM is divided

into four array segments. One-quarter, one-half, or all of the

memory segments can be protected. Any data within the

protected segment is read only. Table 4 shows the function of

block protect bits.

Table 4. Block Write Protect Bits

Level

0

1 (1/4)

2 (1/2)

3 (All)

Status Register Bits

Array Addresses Protected

BP1

BP0

0

0

None

0

1

0x18000–0x1FFFF

1

0

0x10000–0x1FFFF

1

1

0x00000–0x1FFFF

Hardware Write Protection (WP Pin)

The write protect pin (WP) is used to provide hardware write

protection. WP pin allows all normal read and write operations

when held HIGH. When the WP pin is brought LOW and WPEN

bit is ‘1’, all write operations to the Status Register are inhibited.

The hardware write protection function is blocked when the

WPEN bit is ‘0’. This allows the user to install the CY14B101P in

a system with the WP pin tied to ground, and still write to the

Status Register.

WP pin can be used along with WPEN and block protect bits

(BP1 and BP0) of the Status Register to inhibit writes to memory.

When WP pin is LOW and WPEN is set to ‘1’, any modifications

to Status Register are disabled. Therefore, the memory is

protected by setting the BP0 and BP1 bits and the WP pin inhibits

any modification of the Status Register bits, providing hardware

write protection.

Note WP going LOW when CS is still LOW has no effect on any

of the ongoing write operations to the Status Register.

Table 5 summarizes all the protection features provided in the

CY14B101P.

Table 5. Write Protection Operation

WPEN WP

X

X

0

X

1 LOW

1 HIGH

WEN

Protected Unprotected

Blocks

Blocks

Status

Register

0 Protected Protected Protected

1 Protected Writable Writable

1 Protected Writable Protected

1 Protected Writable Writable

Memory Access

All memory accesses are done using the READ and WRITE

instructions. These instructions cannot be used while a STORE

or RECALL cycle is in progress. A STORE cycle in progress is

indicated by the RDY bit of the Status Register and the HSB pin.

Read Sequence (READ) instruction

The read operations on CY14B101P are performed by giving the

instruction on the SI pin and reading the output on SO pin. The

following sequence needs to be followed for a read operation:

After the CS line is pulled LOW to select a device, the read

opcode is transmitted through the SI line followed by three bytes

of address. The most significant address byte contains A16 in

bit 0 and other bits as don’t cares. Address bits A15 to A0 are

sent in the following two address bytes. After the last address bit

is transmitted on the SI pin, the data (D7 - D0) at the specific

address is shifted out on the SO line on the falling edge of SCK

starting with D7. Any other data on SI line after the last address

bit is ignored.

CY14B101P allows reads to be performed in bursts through SPI

which can be used to read consecutive addresses without

issuing a new READ instruction. If only one byte is to be read,

the CS line must be driven HIGH after one byte of data comes

out. However, the read sequence may be continued by holding

the CS line LOW and the address is automatically incremented

and data continues to shift out on SO pin. When the last data

memory address (0x1FFFF) is reached, the address rolls over to

0x0000 and the device continues to read.

Write Sequence (WRITE) instruction

The write operations on CY14B101P are performed through the

SI pin. To perform a write operation CY14B101P, if the device is

write disabled, then the device must first be write enabled

through the WREN instruction. When the writes are enabled

(WEN = ‘1’), WRITE instruction is issued after the falling edge of

CS. A WRITE instruction constitutes transmitting the WRITE

opcode on SI line followed by 3-bytes of address and the data

(D7-D0) which is to be written. The Most Significant address byte

contains A16 in bit 0 with other bits being don’t cares. Address

bits A15 to A0 are sent in the following two address bytes.

CY14B101P allows writes to be performed in bursts through SPI

which can be used to write consecutive addresses without

issuing a new WRITE instruction. If only one byte is to be written,

the CS line must be driven HIGH after the D0 (LSB of data) is

transmitted. However, if more bytes are to be written, CS line

must be held LOW and address incremented automatically. The

following bytes on the SI line are treated as data bytes and

written in the successive addresses. When the last data memory

Document Number: 001-44109 Rev. *M

Page 11 of 36

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