CY14B101NA Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B101NA Datasheet PDF : 24 Pages
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PRELIMINARY
CY14B101LA, CY14B101NA
Pinouts (continued)
Figure 3. Pin Diagram - 54-Pin TSOP II
NC
[7]
1
NC 2
A0 3
A1 4
54 HSB
53 NC [6]
52 NC[5]
51 NC[4]
A2 5
A3 6
50 A15
49 OE
A4 7
48 BHE
CE 8
47 BLE
DQ0 9
46 DQ15
DQ1 10 54 - TSOP II 45
DQ2 11
(x16)
44
DQ3 12
43
VCC 13
Top View
42
VSS 14 (not to scale) 41
DQ14
DQ13
DQ12
VSS
VCC
DQ4 15
DQ5 16
DQ6 17
DQ7 18
WE 19
A5 20
A6 21
A7 22
A8 23
A9 24
NC 25
40
DQ11
39 DQ10
38 DQ9
37 DQ8
36
VCAP
35
A14
34 A13
33 A12
32 A11
31 A10
30 NC
NC 26
29 NC
NC 27
28 NC
Table 1. Pin Definitions
Pin Name I/O Type
Description
A0 – A16
A0 – A15
Input
Address Inputs Used to Select one of the 131,072 Bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 65,536 Words of the nvSRAM for x16 Configuration.
DQ0 – DQ7
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation.
DQ0 – DQ15 Input/Output Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
WE
CE
OE
BHE
BLE
VSS
VCC
HSB[8]
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
Input
Input
Ground
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Ground for the Device. Must be connected to the ground of the system.
Power Power Supply Inputs to the Device. 3.0V +20%, –10%
Supply
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is
driven HIGH for short time with standard output high current.
VCAP
NC
Power AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
Supply nonvolatile elements.
No Connect No Connect. This pin is not connected to the die.
Document #: 001-42879 Rev. *C
Page 3 of 24
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