CY14B101I-SFXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B101I-SFXI Datasheet PDF : 42 Pages
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PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
Command Register
The Command Register resides at address ‘AA’ of the Control
Registers Slave device. This is a write only register. The byte
written to this register initiates a STORE, RECALL, AutoStore
Enable, AutoStore Disable, and Sleep mode operation as listed
in Table 6. The section Executing Commands using Command
Register on page 20 explains how you can execute Command
Register bytes.
Table 6. Command Register Bytes
Data Byte
[7:0]
0011 1100
0110 0000
0101 1001
0001 1001
1011 1001
Command
Description
STORE
RECALL
ASENB
ASDISB
SLEEP
STORE SRAM data to nonvolatile
memory
RECALL data from nonvolatile
memory to SRAM
Enable AutoStore
Disable AutoStore
Enter Sleep Mode for low power
consumption
■ STORE: Initiates nvSRAM Software STORE. The nvSRAM
cannot be accessed for tSTORE time after this instruction has
been executed. When initiated, the device performs a STORE
operation regardless of whether or not a write has been
performed since the last NV operation. After the tSTORE cycle
time is completed, the SRAM is activated again for read/write
operations.
■ RECALL: Initiates nvSRAM Software RECALL. The nvSRAM
cannot be accessed for tRECALL time after this instruction has
been executed. The RECALL operation does not alter the data
in the nonvolatile elements. A RECALL may be initiated in two
ways: Hardware RECALL, initiated on power-up; and Software
RECALL, initiated by a I2C RECALL instruction.
■ ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be
accessed for tSS time after this instruction has been executed.
This setting is not nonvolatile and needs to be followed by a
manual STORE sequence if this is desired to survive the power
cycle. The part comes from the factory with AutoStore Enabled.
■ ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot
be accessed for tSS time after this instruction has been
executed. This setting is not nonvolatile and needs to be
followed by a manual STORE sequence if this is desired to
survive power cycle.
Note If AutoStore is disabled and VCAP is not required, it is
required that the VCAP pin is left open. VCAP pin must never be
connected to ground. Power Up RECALL operation cannot be
disabled in any case.
■ SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode.
When the SLEEP instruction is registered, the nvSRAM
performs a STORE operation to secure the data to nonvolatile
memory and then enters into sleep mode. Whenever nvSRAM
enters into sleep mode, it initiates non volatile STORE cycle
which results in losing an endurance cycle per sleep command
execution. A STORE cycle starts only if a write to the SRAM
has been performed since the last STORE or RECALL cycle.
The nvSRAM enters into sleep mode in this manner:
1. The master sends a START command.
2. The master sends Control Registers Slave device ID with I2C
write bit set (R/W = ’0’).
3. The slave (nvSRAM) sends an ACK back to the master.
4. The master sends Command Register address (0xAA).
5. The slave (nvSRAM) sends an ACK back to the master.
6. The master sends Command Register byte for entering into
sleep mode.
7. The slave (nvSRAM) sends an ACK back to the master.
8. The master generates a STOP condition.
Once in sleep mode, the device starts consuming IZZ current
tSLEEP time after SLEEP instruction is registered. The device is
not accessible for normal operations until it is out of sleep mode.
The nvSRAM wakes up after tWAKE duration after the device
slave address is transmitted by the master.
Transmitting any of the three slave addresses wakes the
nvSRAM from sleep mode. The nvSRAM device is not
accessible during tSLEEP and tWAKE interval and any attempt to
access the nvSRAM device by the master is ignored and
nvSRAM sends NACK to the master. An alternate method of
determining when the device is ready is for the master to send
read or write commands and look for an ACK.
Write Protection (WP)
The Write Protect (WP) pin is an active HIGH pin and protects
the entire memory and all registers from write operations. To
inhibit all the write operations, this pin must be held HIGH. When
this pin is HIGH, all memory and register writes are prohibited
and the address counter is not incremented. This pin is internally
pulled LOW and, therefore, can be left open if not used.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM that
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
STORE or RECALL.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in “Command Register” on page 9. If AutoStore is
enabled without a capacitor on VCAP pin, the device attempts an
AutoStore operation without sufficient charge to complete the
Store. This will corrupt the data stored in nvSRAM
Figure 10 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation. See the DC Electrical
Characteristics on page 31 for the size of the VCAP.
Document #: 001-54391 Rev. *C
Page 9 of 42
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