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CY14B101I-SFXI Datasheet PDF : 42 Pages
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PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
Read Operation
If the last bit of the slave device address is ‘1’, a read operation
is assumed and the nvSRAM takes control of the SDA line
immediately after the slave device address byte is sent out by
the master. The read operation starts from the current address
location (the location following the previous successful write or
read operation). When the last address is reached, the address
counter loops back to the first address.
In case of the Control Register Slave, whenever a burst read is
performed such that it flows to a non-existent address, the reads
operation loops back to 0x00. This is applicable, in particular, for
the Command Register.
Read operation can be ended using the following methods:
1. The master issues a NACK on the ninth clock cycle followed
by a STOP or a Repeated START condition on the tenth clock
cycle.
2. The master generates a STOP or Repeated START condition
on the ninth clock cycle.
More details on write instruction are provided in the section
“Memory Slave Access” on page 11.
Memory Slave Access
The following sections describe the data transfer sequence
required to perform read or write operations from nvSRAM.
Write nvSRAM
Each write operation consists of a slave address being
transmitted after the start condition. The last bit of slave address
must be set as ‘0’ to indicate a Write operation. The master may
write one byte of data or continue writing multiple consecutive
address locations while the internal address counter keeps
incrementing automatically. The address register is reset to
0x00000 after the last address in memory is accessed. The write
operation continues till a STOP or Repeated START condition is
generated by the master or a NACK is issued by the nvSRAM.
A write operation is executed only after nvSRAM receives all the
eight data bits. The nvSRAM sends an ACK signal after a
successful write operation. A write operation may be terminated
by the master by generating a STOP condition or a Repeated
START operation. If the master desires to abort the current write
operation without altering the memory contents, this should be
done using a START/STOP condition prior to the eighth data bit.
If the master tries to access a write protected memory address
on the nvSRAM, a NACK is returned after the data byte intended
to write the protected address is transmitted and address counter
will not be incremented. Similarly, in a burst mode write
operation, a NACK is returned when the data byte that attempts
to write a protected memory location and the address counter is
not incremented.
Figure 11. Single-Byte Write into nvSRAM (except Hs-mode)
By Master
SDA Line
By nvSRAM
S
T
A
R Memory Slave Address
T
S 1 0 1 0 A2 A1 A16 0
A
Address MSB
Address LSB
A
A
Data Byte
S
T
0
P
P
A
Figure 12. Multi-Byte Write into nvSRAM (except Hs-mode)
By Master
SDA Line
By nvSRAM
S
T
A
R Memory Slave Address
T
S 1 0 1 0 A2 A1 A16 0
A
Address MSB
Address LSB
A
A
Data Byte 1
A
S
T
Data Byte N
0
P
P
A
Document #: 001-54391 Rev. *C
Page 11 of 42
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