CY14B101I-SFXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B101I-SFXI Datasheet PDF : 42 Pages
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PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
Hardware STORE and HSB pin Operation
The HSB pin in CY14X101I is used to control and acknowledge
STORE operations. If no STORE or RECALL is in progress, this
pin can be used to request a Hardware STORE cycle. When the
HSB pin is driven LOW, the device conditionally initiates a
STORE operation after tDELAY duration. An actual STORE cycle
starts only if a write to the SRAM has been performed since the
last STORE or RECALL cycle. Reads and Writes to the memory
are inhibited for tSTORE duration or as long as HSB pin is LOW.
The HSB pin also acts as an open drain driver (internal 100 kΩ
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 kΩ pull-up
resistor.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB pin unconnected if not used.
Figure 10. AutoStore Mode
VCC
0.1uF
VCC
VCAP
VSS
VCAP
Hardware RECALL (Power Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated that transfers the content of
nonvolatile memory to the SRAM. The data may have been
previously stored on the nonvolatile memory through a STORE
sequence.
A Power Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin can be
used to detect the ready status of the device.
Write Operation
The last bit of the slave device address indicates a read or a write
operation. In case of a write operation, the slave device address
is followed by the memory or register address and data. A write
operation continues as long as a STOP or Repeated START
condition is generated by the master or if a NACK is issued by
the nvSRAM.
A NACK is issued from the nvSRAM under the following
conditions:
1. A valid Device ID is not received.
2. A write (burst write) access to a protected memory block
address returns a NACK from nvSRAM after the data byte is
received. However, the address counter is set to this address
and the following current read operation starts from this
address.
3. A write/random read access to an invalid or out-of-bound
memory address returns a NACK from the nvSRAM after the
address is received. The address counter remains unchanged
in such a case.
4. A write to the Command Register with an invalid command.
This operation returns a NACK from the nvSRAM.
After a NACK is sent out from the nvSRAM, the write operation
is terminated and any data on the SDA line is ignored till a STOP
or a Repeated START condition is generated by the master.
For example, consider a case where the burst write access is
performed on Control Register Slave address 0x01 for writing the
serial number and continued to the address 0x09, which is a
read-only register. The device returns a NACK and address
counter is not incremented. A following read operation is started
from the address 0x09. Further, any write operation which starts
from a write protected address (say, 0x09) is responded by the
nvSRAM with a NACK after the data byte is sent and set the
address counter to this address. A following read operation starts
from the address 0x09 in this case also.
Note In case you try to read/write access an address that does
not exist (for example 0x0D in Control Register Slave or 0x3F in
RTC registers), nvSRAM responds with a NACK immediately
after the out-of-bound address is transmitted. The address
counter remains unchanged and holds the previous successful
read or write operation address.
A write operation is performed internally with no delay after the
eighth bit of data is transmitted. If a write operation is not
intended, the master must terminate the write operation before
the eighth clock cycle by generating a STOP or Repeated
START condition.
More details on write instructions are provided in the section
“Memory Slave Access” on page 11.
Document #: 001-54391 Rev. *C
Page 10 of 42
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