CY14B101I(2012) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY14B101I
(Rev.:2012)

1-Mbit (128 K × 8) Serial (I2C) nvSRAM with Real Time Clock

Cypress Semiconductor 

PRELIMINARY

CY14C101I

CY14B101I

CY14E101I

Figure 9. Control Registers Slave Device Address

handbook, halfpMagSe B

LSB

0 0 1 1 A2 A1 X R/W

Slave ID

Device

Select

Table 2. Control Registers Map

Address

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0xAA

Description Read/Write

Details

Memory

Control

Register

Read/Write Contains Block

Protect bits and Serial

Number lock bit

Serial Number Read/Write Programmable Serial

8 bytes (Read only Number. Locked by

when SNL setting the Serial

is set) Number lock bit in the

Memory Control

Register to ‘1’.

Device ID Read only Device ID is factory

programmed

Reserved

Command

Register

Reserved

Write only

Reserved

Allows commands for

STORE, RECALL,

AutoStore

Enable/Disable,

SLEEP Mode

Memory Control Register

The Memory Control Register contains the following bits:

Table 3. Memory Control Register Bits

Bit 7

0

Bit 6

SNL

(0)

Bit 5

0

Bit 4

0

Bit 3

BP1

(0)

Bit 2

BP0

(0)

Bit 1

0

Bit 0

0

■ BP1:BP0: Block protect bits are used to protect 1/4, 1/2 or full

memory array. These bits can be written through a write

instruction to the 0x00 location of the Control Register Slave

device. However, any STORE cycle transfers SRAM data into

a nonvolatile cell regardless of whether or not the block is

protected. The default value shipped from the factory for BP0

and BP1 is ‘0’.

Table 4. Block Protection

Level

0

1/4

1/2

1

BP1:BP0

00

01

10

11

Block Protection

None

0x18000–0x1FFFF

0x10000–0x1FFFF

0x00000–0x1FFFF

■ SNL (S/N Lock) Bit: Serial Number Lock bit (SNL) is used to

lock the serial number. Once the bit is set to ‘1’, the serial

number registers are locked and no modification is allowed.

This bit cannot be cleared to ‘0’. The serial number is secured

on the next STORE operation (Software STORE or AutoStore).

If AutoStore is not enabled, user must perform the Software

STORE operation to secure the lock bit status. If a STORE was

not performed, the serial number lock bit will not survive the

power cycle. The default value shipped from the factory for SNL

is ‘0’.

Command Register

The Command Register resides at address ‘AA’ of the Control

Registers Slave device. This is a write only register. The byte

written to this register initiates a STORE, RECALL, AutoStore

Enable, AutoStore Disable, and Sleep mode operation as listed

in Table 5. The section Executing Commands Using Command

Register on page 19 explains how you can execute Command

Register bytes.

Table 5. Command Register Bytes

Data Byte

[7:0]

0011 1100

0110 0000

0101 1001

0001 1001

1011 1001

Command

Description

STORE

RECALL

ASENB

ASDISB

SLEEP

STORE SRAM data to nonvolatile

memory

RECALL data from nonvolatile

memory to SRAM

Enable AutoStore

Disable AutoStore

Enter Sleep Mode for low power

consumption

■ STORE: Initiates nvSRAM Software STORE. The nvSRAM

cannot be accessed for tSTORE time after this instruction has

been executed. When initiated, the device performs a STORE

operation regardless of whether or not a write has been

performed since the last NV operation. After the tSTORE cycle

time is completed, the SRAM is activated again for read/write

operations.

■ RECALL: Initiates nvSRAM Software RECALL. The nvSRAM

cannot be accessed for tRECALL time after this instruction has

been executed. The RECALL operation does not alter the data

in the nonvolatile elements. A RECALL may be initiated in two

ways: Hardware RECALL, initiated on power-up; and Software

RECALL, initiated by a I2C RECALL instruction.

■ ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be

accessed for tSS time after this instruction has been executed.

This setting is not nonvolatile and needs to be followed by a

manual STORE sequence if this is desired to survive the power

cycle. The part comes from the factory with AutoStore Enabled

and 0x00 written in all cells.

■ ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot

be accessed for tSS time after this instruction has been

executed. This setting is not nonvolatile and needs to be

followed by a manual STORE sequence if this is desired to

survive power cycle.

Note If AutoStore is disabled and VCAP is not required, it is

required that the VCAP pin is left open. VCAP pin must never be

Document Number: 001-54391 Rev. *G

Page 8 of 41

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