CY14B101MA Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B101MA Datasheet PDF : 29 Pages
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PRELIMINARY
CY14B101KA/CY14B101MA
Pinouts
Figure 1. Pin Diagram - 44-Pin, 54-Pin TSOP II, and 48-Pin SSOP
INT
NC[7
1
2
A0 3
A1 4
A2 5
44 HSB
43 NC[6]
42 NC[5]
41 NC[4]
40 NC
A3 6
39 A16
A4 7
38 A15
CE 8
37 OE
DQ0 9 44 - TSOP II 36 DQ7
DQ1 10
(x8)
35 DQ6
VCC 11 Top View
34 VSS
VSS 12 (not to scale) 33 VCC
DQ2 13
32 DQ5
DQ3 14
31 DQ4
WE 15
A5 16
30 VCAP
29 A14
VCAP 1
48
A16 2
47
A14 3
46
A12 4
45
A7 5
44
A6 6
43
A5 7
42
INT 8
A4 9
41
48 - SSOP 40
NC 10
(x8)
39
NC 11 Top View
38
NC
VSS
12
13
(not to scale)
37
36
NC 14
35
VRTCbat
15
34
DQ0 16
33
A3 17
32
VCC
A15
HSB
WE
A13
A8
A9
NC
A11
NC
NC
NC
VSS
NC
VRTCcap
DQ6
OE
A6 17
A7 18
28 A13
27 A12
A2 18
A1 19
31 A10
30 CE
A8 19
26 A11
A0 20
29 DQ7
A9 20
25 A10
DQ1 21
28 DQ5
Xout 21
Xin 22
24 VRTCcap
23 VRTCbat
DQ2 22
Xout 23
Xin 24
27 DQ4
26 DQ3
25 VCC
IN[7T] 1
54
NC 2
53
A0 3
52
A1 4
51
A2 5
50
A3 6
49
A4 7
48
CE 8
47
DQ0 9
46
DQ1 10 54 - TSOP II 45
DQ2 11
(x16)
44
DQ3 12
43
VCC 13 Top View
42
VSS 14 (not to scale) 41
DQ4 15
40
DQ5 16
39
DQ6 17
38
DQ7 18
37
WE 19
36
A5 20
35
A6 21
34
A7 22
33
A8 23
32
A9 24
31
NC 25
30
Xout 26
29
Xin 27
28
HNSCB[6]
[5]
NC [4]
NC
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ 11
DQ 10
DQ9
DQ 8
VCAP
A14
A13
A12
A11
A10
NC
VRTCcap
VRTCbat
Pin Definitions
Pin Name I/O Type
Description
A0 – A16
A0 – A15
DQ0 – DQ7
DQ0 – DQ15
Input
Input/Output
Address Inputs Used to Select one of the 131,072 Bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 65,536 Words of the nvSRAM for x16 Configuration.
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on
operation.
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
NC
No Connect No Connects. This pin is not connected to the die.
WE
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is
written to the specific address location.
CE
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
OE
cycles. Deasserting OE HIGH causes the I/O pins to tristate.
BHE
Input Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Xout
Xin
VRTCcap
VRTCbat
Output Crystal Connection. Drives crystal on start up.
Input Crystal Connection. For 32.768 kHz crystal.
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used.
Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used.
Notes
4. Address expansion for 2 Mbit. NC pin not connected to die.
5. Address expansion for 4 Mbit. NC pin not connected to die.
6. Address expansion for 8 Mbit. NC pin not connected to die.
7. Address expansion for 16 Mbit. NC pin not connected to die.
Document #: 001-42880 Rev. *C
Page 2 of 29
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