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CY14B101MA Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY14B101MA Datasheet PDF : 29 Pages
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PRELIMINARY
CY14B101KA/CY14B101MA
1 Mbit (128K x 8/64K x 16) nvSRAM with
Real Time Clock
Features
1 Mbit nvSRAM
20 ns, 25 ns, and 45 ns access times
Internally organized as 128K x 8 (CY14B101KA) or 64K x 16
(CY14B101MA)
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power down
RECALL to SRAM initiated on power up or by software
High Reliability
Infinite Read, Write, and RECALL cycles
200,000 STORE cycles to QuantumTrap
20 year data retention
Real Time Clock
Full featured Real Time Clock
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Backup current of 300 nA
Industry Standard Configurations
Single 3V +20%, –10% operation
Commercial and Industrial temperatures
44-pin and 54-pin TSOP II and 48-pin SSOP packages
Pb-free and RoHS compliance
Functional Description
The Cypress CY14B101KA/CY14B101MA combines a 1 Mbit
nonvolatile static RAM with a full featured real time clock in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written an infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy oscillator.
The alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
Logic Block Diagram[1, 2, 3]
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Quatrum
Trap
VCC
VCA
P
1024 X 1024
R
O
STORE
POWER
CONTROL
VRTCbat
VRTCcap
W
RECALL
D
E
STATIC RAM
C
ARRAY
O
1024 X 1024
D
E
R
STORE/RECALL
CONTROL
SOFTWARE
DETECT
HSB
A14 - A2
I
N
P
U
T
B
COLUMN I/O
U
F
F
E
R
COLUMN DEC
S
A0 A1 A2 A3 A4 A10 A11
RTC
MUX
Xout
Xin
INT
A16- A0
OE
WE
CE
BLE
BHE
Notes
1. Address A0 - A16 for x8 configuration and Address A0 - A15 for x16 configuration.
2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-42880 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 09, 2009
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