CY14B101MA(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

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Fabricante

CY14B101MA
(Rev.:2011)

1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock

Cypress Semiconductor 

CY14B101KA

CY14B101MA

Device Operation

The CY14B101KA/CY14B101MA nvSRAM is made up of two

functional components paired in the same physical cell. These

are a SRAM memory cell and a nonvolatile QuantumTrap cell.

The SRAM memory cell operates as a standard fast static RAM.

Data in the SRAM is transferred to the nonvolatile cell (the

STORE operation), or from the nonvolatile cell to the SRAM (the

RECALL operation). Using this unique architecture, all cells are

stored and recalled in parallel. During the STORE and RECALL

operations SRAM read and write operations are inhibited. The

CY14B101KA/CY14B101MA supports infinite reads and writes

similar to a typical SRAM. In addition, it provides infinite RECALL

operations from the nonvolatile cells and up to 1 million STORE

operations. Refer Truth Table For SRAM Operations on page 26

for a complete description of read and write modes.

SRAM Read

The CY14B101KA/CY14B101MA performs a read cycle

whenever CE and OE are LOW, and WE and HSB are HIGH.

The address specified on pins A0–16 or A0–15 determines which

of the 131,072 data bytes or 65,536 words of 16 bits each are

accessed. Byte enables (BHE, BLE) determine which bytes are

enabled to the output, in the case of 16-bit words. When the read

is initiated by an address transition, the outputs are valid after a

delay of tAA (read cycle #1). If the read is initiated by CE or OE,

the outputs are valid at tACE or at tDOE, whichever is later (read

cycle #2). The data output repeatedly responds to address

changes within the tAA access time without the need for

transitions on any control input pins. This remains valid until

another address change or until CE or OE is brought HIGH, or

WE or HSB is brought LOW.

SRAM Write

A write cycle is performed when CE and WE are LOW and HSB

is HIGH. The address inputs must be stable before entering the

write cycle and must remain stable until CE or WE goes HIGH at

the end of the cycle. The data on the common I/O pins IO0–7 are

written into the memory if it is valid tSD before the end of a

WE-controlled write, or before the end of an CE-controlled write.

The Byte Enable inputs (BHE, BLE) determine which bytes are

written, in the case of 16-bit words. It is recommended that OE

be kept HIGH during the entire write cycle to avoid data bus

contention on common I/O lines. If OE is left LOW, internal

circuitry turns off the output buffers tHZWE after WE goes LOW.

AutoStore Operation

The CY14B101KA/CY14B101MA stores data to the nvSRAM

using one of three storage operations. These three operations

are: Hardware STORE, activated by the HSB; Software STORE,

activated by an address sequence; AutoStore, on device

power-down. The AutoStore operation is a unique feature of

QuantumTrap technology and is enabled by default on the

CY14B101KA/CY14B101MA.

During a normal operation, the device draws current from VCC to

charge a capacitor connected to the VCAP pin. This stored

charge is used by the chip to perform a single STORE operation.

If the voltage on the VCC pin drops below VSWITCH, the part

automatically disconnects the VCAP pin from VCC. A STORE

operation is initiated with power provided by the VCAP capacitor.

Note If the capacitor is not connected to VCAP pin, AutoStore

must be disabled using the soft sequence specified in Preventing

AutoStore on page 7. In case AutoStore is enabled without a

capacitor on VCAP pin, the device attempts an AutoStore

operation without sufficient charge to complete the Store. This

corrupts the data stored in nvSRAM.

Figure 2. AutoStore Mode

VCC

0.1 uF

VCC

WE

VCAP

VSS

VCAP

Figure 2 shows the proper connection of the storage capacitor

(VCAP) for automatic STORE operation. Refer to DC Electrical

Characteristics on page 17 for the size of the VCAP. The voltage

on the VCAP pin is driven to VCC by a regulator on the chip. A

pull-up should be placed on WE to hold it inactive during

power-up. This pull-up is only effective if the WE signal is tristate

during power-up. Many MPUs tristate their controls on power-up.

This should be verified when using the pull-up. When the

nvSRAM comes out of power-on-RECALL, the MPU must be

active or the WE held inactive until the MPU comes out of reset.

To reduce unnecessary nonvolatile stores, AutoStore and

Hardware STORE operations are ignored unless at least one

write operation has taken place since the most recent STORE or

RECALL cycle. Software initiated STORE cycles are performed

regardless of whether a write operation has taken place.

The HSB signal is monitored by the system to detect if an

AutoStore cycle is in progress.

Hardware STORE (HSB) Operation

The CY14B101KA/CY14B101MA provides the HSB pin to

control and acknowledge the STORE operations. The HSB pin

is used to request a Hardware STORE cycle. When the HSB pin

is driven LOW, the CY14B101KA/CY14B101MA conditionally

initiates a STORE operation after tDELAY. An actual STORE cycle

begins only if a write to the SRAM has taken place since the last

STORE or RECALL cycle. The HSB pin also acts as an open

drain driver (internal 100 k weak pull-up resistor) that is inter-

nally driven LOW to indicate a busy condition when the STORE

(initiated by any means) is in progress.

Note After each Hardware and Software STORE operation HSB

is driven HIGH for a short time (tHHHD) with standard output high

Document #: 001-42880 Rev. *I

Page 5 of 34

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