CXK5T8512TM Ver la hoja de datos (PDF) - Sony Semiconductor

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Fabricante

CXK5T8512TM

65536-word × 8-bit High Speed CMOS Static RAM

Sony Semiconductor 

CXK5T8512TM/TN

• Read cycle (WE = “H”)

VCC = 2.7 to 3.6V

VCC = 3.3V ± 0.3V

Item

Symbol -10LLX

-12LLX

-10LLX

-12LLX Unit

Min. Max. Min. Max. Min. Max. Min. Max.

Read cycle time

tRC

100 — 120 — 85 — 100 — ns

Address access time

tAA

— 100 — 120 — 85 — 100 ns

Chip enable access time (CE1)

tCO1

— 100 — 120 — 85 — 100 ns

Chip enable access time (CE2)

tCO2

— 100 — 120 — 85 — 100 ns

Output enable to output valid

tOE

— 50 — 60 — 40 — 50 ns

Output hold from address change

tOH

10 — 10 — 10 — 10 — ns

Chip enable to output in low Z

(CE1, CE2)

tLZ1

tLZ2

10 — 10 — 10 — 10 — ns

Output enable to output in low Z (OE) tOLZ

5 — 5 — 5 — 5 — ns

Chip disable to output in high Z

(CE1, CE2)

tHZ1∗1

tHZ2∗1

—

40

—

40

—

35

—

40 ns

Output disable to output in high Z (OE) tOHZ∗1 — 35 — 35 — 30 — 35 ns

∗1 tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not

referred to as output voltage levels.

• Write cycle

VCC = 2.7 to 3.6V

VCC = 3.3V ± 0.3V

Item

Symbol -10LLX

-12LLX

-10LLX

-12LLX Unit

Min. Max. Min. Max. Min. Max. Min. Max.

Write cycle time

tWC 100 — 120 — 85 — 100 — ns

Address valid to end of write

tAW

80 — 100 — 70 — 80 — ns

Chip enable to end of write

tCW

80 — 100 — 70 — 80 — ns

Data to write time overlap

tDW

40 — 50 — 35 — 40 — ns

Data hold from write time

tDH

0 — 0 — 0 — 0 — ns

Write pulse width

tWP

70 — 70 — 60 — 70 — ns

Address setup time

tAS

0 — 0 — 0 — 0 — ns

Write recovery time (WE)

tWR

5 — 5 — 5 — 5 — ns

Write recovery time (CE1, CE2)

tWR1

5 — 5 — 5 — 5 — ns

Output active from end of write

Write to output in high Z

tOW

5 — 5 — 5 — 5 — ns

tWHZ∗2 — 40 — 40 — 35 — 40 ns

∗2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as

output voltage level.

–5–

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