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componentes Descripción

Fabricante

CXK58512M

65536-word × 8-bit High Speed CMOS Static RAM

Sony Semiconductor 

CXK58512TM/M

• Read cycle (WE = "H")

(Vcc = 5V ± 10%, GND = 0V, Ta = 0 to +70°C)

-55LL

-70LL

-10LL

Item

Symbol

Unit

Min. Max. Min. Max. Min. Max.

Read cycle time

tRC

55 — 70 — 100 — ns

Address access time

tAA

— 55 — 70 — 100 ns

Chip enable access time (CE1)

tCO1

— 55 — 70 — 100 ns

Chip enable access time (CE2)

tCO2

— 55 — 70 — 100 ns

Output enable to output valid

tOE

— 30 — 40 — 50 ns

Output hold from address change

tOH

15 — 15 — 15 — ns

Chip enable to output in low Z (CE1, CE2) tLZ1, tLZ2

10 — 10 — 10 — ns

Output enable to output in low Z (OE)

tOLZ

5

—

5—

5 — ns

Chip disable to output in high Z (CE1, CE2) tHZ1∗, tHZ2∗ —

25

— 25

— 35 ns

Output disable to output in high Z (OE)

tOHZ∗

— 25 — 25 — 35 ns

∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not

referred to as output voltage levels.

• Write cycle

(Vcc = 5V ± 10%, GND = 0V, Ta = 0 to +70°C)

-55LL

-70LL

-10LL

Item

Symbol

Unit

Min. Max. Min. Max. Min. Max.

Write cycle time

tWC

55 — 70 — 100 — ns

Address valid to end of write

tAW

50 — 60 — 70 — ns

Chip enable to end of write

tCW

50 — 60 — 70 — ns

Data to write time overlap

tDW

25 — 30 — 40 — ns

Data hold from write time

tDH

0

—

0—

0 — ns

Write pulse width

tWP

40 — 50 — 70 — ns

Address setup time

tAS

0

—

0—

0 — ns

Write recovery time (WE)

tWR

0

—

0—

0 — ns

Write recovery time (CE1, CE2)

tWR1

0

—

0—

0 — ns

Output active from end of write

Write to output in high Z

tOW

tWHZ∗

10 — 10 — 10 — ns

— 25 — 25 — 30 ns

∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as

output voltage level.

–5–

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