(3) SCLK, XSCEN, SWDT, SRDT pins
(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item
Symbol
Min.
Clock period
tCW
200
Clock pulse width, high tCWH
100
Clock pulse width, low
tCWL
100
Enable signal pulse width tCSWH
170
Enable signal setup time tCSS
0
Enable signal hold time tCSH
100
SWDT Setup time
tWSU
20
SWDT Hold time
tWHD
100
Typ.
—
—
—
—
—
—
—
—
XSCEN
tCSS
tCW
tCWL tCWH
CXD4016R
Max.
Unit
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
tCSH tCSWH
SCLK
SWDT
tWSU tWHD
An example of data read phase
(4) CSOD pin
(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item
Symbol
Min.
CSOD pulse width
tCSOD
260
Typ.
—
CSOD
tCSOD
(5) XRST pin
(VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C)
Item
Symbol
Min.
XRST pulse width
tXRST
100.0
Typ.
—
XRST
tXRST
Max.
Unit
—
µs
Max.
Unit
—
ns
-9-