CXK581000AM Ver la hoja de datos (PDF) - Sony Semiconductor

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Fabricante

CXK581000AM

131072-word × 8-bit High Speed CMOS Static RAM

Sony Semiconductor 

CXK581000ATM/AYM/AM/AP

• Read cycle (WE = "H")

-55LL/55SL -70LL/70SL -10LL/10SL

Item

Symbol Min. Max. Min. Max. Min. Max. Unit

Read cycle time

Address access time

tRC

55 — 70 — 100 —

tAA

— 55 — 70 — 100

Chip enable access time (CE1)

tCO1

— 55 — 70 — 100

Chip enable access time (CE2)

tCO2

— 55 — 70 — 100

Output enable to output valid

Output hold from address change

tOE

—

30 —

40

—

50 ns

tOH

15 — 15 — 15 —

Chip enable to output in low Z (CE1, CE2) tLZ1, tLZ2 10

—

10

—

10

—

Output enable to output in low Z (OE)

tOLZ

5

—5

—

5

—

Chip disable to output in high Z (CE1, CE2) tHZ1, tHZ2∗ —

25

—

25

—

35

Output disable to output in high Z (OE)

tOHZ∗

— 25 — 25 — 35

∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not

referred to as output voltage levels.

• Write cycle

-55LL/55SL -70LL/70SL -10LL/10SL

Item

Symbol Min. Max. Min. Max. Min. Max. Unit

Write cycle time

Address valid to end of write

Chip enable to end of write

Data to write time overlap

Data hold from write time

Write pulse width

Address setup time

Write recovery time (WE)

Write recovery time (CE1, CE2)

Output active from end of write

Write to output in high Z

tWC

tAW

tCW

tDW

tDH

tWP

tAS

tWR

tWR1

tOW

tWHZ∗

55 — 70 — 100 —

50 — 60 — 70 —

50 — 60 — 70 —

25 — 30 — 40 —

0

—

0—

0

— ns

40 — 50 — 70 —

0

—

0—

0

—

0

—

0—

0

—

0

—

0—

0

—

10 — 10 — 10 —

— 25 — 25 — 30

∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as

output voltage level.

–5–

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