CXD2598 Ver la hoja de datos (PDF) - Sony Semiconductor
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CXD2598 Datasheet PDF : 147 Pages
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§1. CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
CLOK
750ns or more
CXD2598Q
DATA
D0 D1
XLAT
Registers
D18 D19 D20 D21 D22 D23
750ns or more
Valid
• The internal registers are initialized by a reset when XRST = 0.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
4 to 6
7
8
9
A
B
C
D
E
Total bit length
8 bits
8 to 24 bits
16 bits
20 bits
32 bits
32 bits
28 bits
24 bits
28 bits
20 bits
20 bits
– 15 –
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